|
|
1 | (10) |
|
1.1 Fundamentals of Video Compression |
|
|
1 | (4) |
|
|
2 | (1) |
|
|
3 | (1) |
|
|
4 | (1) |
|
1.1.4 Motion Estimation and Compensation |
|
|
4 | (1) |
|
|
5 | (1) |
|
1.3 Challenges Encountered |
|
|
6 | (1) |
|
1.4 Contributions of the Present Research |
|
|
7 | (1) |
|
1.5 Organization of the Book |
|
|
8 | (3) |
|
|
8 | (3) |
|
2 Background and Literature Survey |
|
|
11 | (14) |
|
2.1 Block Matching Algorithm |
|
|
11 | (8) |
|
2.1.1 Full Search Block Matching Algorithm |
|
|
12 | (1) |
|
2.1.2 Fast Search Algorithms for Block Matching Algorithm |
|
|
13 | (4) |
|
2.1.3 Motion Estimation Architectures |
|
|
17 | (2) |
|
2.2 Scalable Video Coding |
|
|
19 | (2) |
|
|
21 | (4) |
|
|
21 | (4) |
|
3 VLSI Architecture for Fast Three Step Search Algorithm |
|
|
25 | (10) |
|
|
25 | (1) |
|
3.2 Prediction of Direction of Current Motion Vector |
|
|
26 | (1) |
|
3.3 Fast Three Step Search Algorithm (FTSS) |
|
|
27 | (1) |
|
3.4 Proposed 3-PE Architecture for FTSS |
|
|
28 | (4) |
|
|
32 | (2) |
|
|
32 | (1) |
|
|
33 | (1) |
|
|
34 | (1) |
|
|
34 | (1) |
|
4 Parallel Architecture for Successive Elimination Block Matching Algorithm |
|
|
35 | (10) |
|
|
35 | (1) |
|
4.2 Successive Elimination Algorithm (SEA) |
|
|
36 | (1) |
|
4.3 Proposed Parallel Architecture for SEA |
|
|
37 | (5) |
|
4.3.1 Internal Memory Unit (IMU) |
|
|
38 | (1) |
|
|
38 | (1) |
|
4.3.3 Process Control Unit (PCU) |
|
|
39 | (1) |
|
4.3.4 Working of the Proposed Architecture |
|
|
39 | (3) |
|
|
42 | (2) |
|
|
42 | (1) |
|
|
43 | (1) |
|
|
44 | (1) |
|
|
44 | (1) |
|
5 Fast One-Bit Transformation Architectures |
|
|
45 | (20) |
|
|
45 | (2) |
|
5.2 One Bit Transformation and Diamond Search Algorithm |
|
|
47 | (4) |
|
5.2.1 One Bit Transformation Based ME |
|
|
47 | (1) |
|
5.2.2 Diamond Search Based 1-BT ME |
|
|
48 | (3) |
|
5.3 Data Flow Analysis for DS Algorithm |
|
|
51 | (2) |
|
5.4 Proposed VLSI Architecture for 1-BT Based Fixed Block Size Motion Estimation |
|
|
53 | (5) |
|
|
54 | (1) |
|
5.4.2 Memory Interleaving |
|
|
55 | (1) |
|
5.4.3 Register Array for the Current Block Pixels |
|
|
56 | (1) |
|
5.4.4 Search Register Array |
|
|
56 | (1) |
|
|
57 | (1) |
|
5.4.6 Process Control Unit |
|
|
57 | (1) |
|
5.5 Proposed Fast Binary ME Architecture for Variable Block Size |
|
|
58 | (2) |
|
|
60 | (2) |
|
5.6.1 Performance of the Proposed Fast 1-BT Based ME |
|
|
60 | (1) |
|
5.6.2 Implementation Results |
|
|
61 | (1) |
|
|
62 | (3) |
|
|
63 | (2) |
|
6 Efficient Pixel Truncation Algorithm and Architecture |
|
|
65 | (20) |
|
|
65 | (1) |
|
6.2 Proposed Fast Two Stage Search Based Motion Estimation Algorithm |
|
|
66 | (3) |
|
6.2.1 Summary of the Proposed Fast Two Stage Search Algorithm |
|
|
68 | (1) |
|
6.3 Architecture for the Proposed Fast Two Stage Search Algorithm |
|
|
69 | (8) |
|
6.3.1 Memory Management for the Proposed F2SS Algorithm |
|
|
69 | (1) |
|
6.3.2 Proposed Architecture for the First Stage of ME |
|
|
70 | (2) |
|
6.3.3 Proposed Architecture for the Second Stage of ME |
|
|
72 | (5) |
|
|
77 | (5) |
|
6.4.1 Performance Analysis of the Proposed Algorithm |
|
|
77 | (3) |
|
6.4.2 Synthesis Results and Comparison |
|
|
80 | (2) |
|
|
82 | (3) |
|
|
82 | (3) |
|
7 Introduction to Scalable Image and Video Coding |
|
|
85 | (24) |
|
7.1 Overview of Wavelet Based Scalable Video Coding |
|
|
85 | (11) |
|
7.1.1 Existing Scalable Video Codec Designs |
|
|
86 | (3) |
|
7.1.2 Discrete Wavelet Transform |
|
|
89 | (1) |
|
7.1.3 Problem of Shift Variance in DWT |
|
|
89 | (2) |
|
7.1.4 Critically Sampled DWT |
|
|
91 | (1) |
|
7.1.5 Over-Complete Discrete Wavelet Transform (ODWT) |
|
|
91 | (1) |
|
7.1.6 Lifting Based Discrete Wavelet Transform |
|
|
92 | (2) |
|
7.1.7 Over-Complete Discrete Wavelet Transform Using the Lifting Scheme |
|
|
94 | (1) |
|
7.1.8 Spatial Scalability with DWT |
|
|
94 | (1) |
|
7.1.9 Temporal Scalability with DWT |
|
|
95 | (1) |
|
7.2 Motion Compensated Temporal Filtering (MCTF) |
|
|
96 | (6) |
|
7.2.1 Spatial Domain MCTF (SD-MCTF) |
|
|
97 | (1) |
|
7.2.2 In-Band MCTF (IB-MCTF) |
|
|
98 | (4) |
|
7.3 Proposed Framework for SVC |
|
|
102 | (2) |
|
|
104 | (2) |
|
|
106 | (3) |
|
|
107 | (2) |
|
|
109 | (4) |
|
8.1 SoC Based Design for SVC |
|
|
109 | (1) |
|
8.2 Scalable Extension of HEVC |
|
|
110 | (3) |
|
|
111 | (2) |
Appendix A Matlab Programs |
|
113 | (12) |
Appendix B Verilog Modules |
|
125 | (30) |
Index |
|
155 | |