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E-raamat: Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

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Multi-Objective Optimization in Physical Synthesis of Integrated CircuitsSuurem pilt
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As well as explaining how to integrate chip optimizations in powerful new ways, this comprehensive introduction to physical synthesis takes the reader methodically from first principles to state-of-the-art optimizations used in cutting-edge industrial tools.

This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products. It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements.
Part I Introduction and Prior Art
1 Timing Closure for Multi-Million-Gate Integrated Circuits
3(8)
1.1 Challenges in Physical Synthesis
3(2)
1.2 Our Contributions
5(3)
1.3 Organization of the Book
8(3)
References
8(3)
2 State of the Art in Physical Synthesis
11(10)
2.1 Progression of a Modern Physical-Synthesis Flow
11(2)
2.2 The Controller/Transformation Approach
13(1)
2.3 Circuit Delay Estimation
14(2)
2.4 Current Trends in Physical Synthesis
16(5)
References
17(4)
Part II Local Physical Synthesis and Necessary Analysis Techniques
3 Buffer Insertion During Timing-Driven Placement
21(26)
3.1 Introduction
21(3)
3.2 Background
24(1)
3.3 The RUMBLE Timing Model
25(4)
3.4 Timing-Driven Placement with Buffering
29(5)
3.5 The-RUMBLE Algorithm
34(4)
3.6 Empirical Validation
38(7)
3.7 Conclusions
45(2)
References
45(2)
4 Bounded Transactional Timing Analysis
47(18)
4.1 Introduction
47(2)
4.2 Background
49(6)
4.3 Transactional Timing Analysis
55(5)
4.4 Empirical Validation
60(1)
4.5 Conclusions
61(4)
References
62(3)
5 Gate Sizing During Timing-Driven Placement
65(18)
5.1 Introduction
65(3)
5.2 Background
68(1)
5.3 Problem Formulation
68(4)
5.4 Our Simultaneous Placement and Gate-Sizing Algorithm
72(5)
5.5 Empirical Validation
77(2)
5.6 Conclusions
79(4)
References
79(4)
Part III Broadening the Scope of Circuit Transformations
6 Physically-Driven Logic Restructuring
83(22)
6.1 Introduction
83(3)
6.2 Background and Preliminaries
86(2)
6.3 Fast Timing-Driven Gate Cloning
88(9)
6.4 Empirical Validation
97(3)
6.5 Extensions
100(2)
6.6 Conclusions
102(3)
References
103(2)
7 Logic Restructuring as an Aid to Physical Retiming
105(18)
7.1 Introduction
105(2)
7.2 Background, Notation and Objectives
107(3)
7.3 Joint Optimization for Physical Synthesis
110(8)
7.4 Empirical Validation
118(2)
7.5 Extensions
120(1)
7.6 Conclusions
121(2)
References
122(1)
8 Broadening the Scope of Optimization Using Partitioning
123(10)
8.1 Introduction
123(1)
8.2 Background
124(1)
8.3 Forming Subcircuits Using Top-Down Netlist Partitioning
125(2)
8.4 Trade-Offs in Window Selection
127(2)
8.5 Empirical Validation
129(2)
8.6 Conclusions
131(2)
References
132(1)
9 Co-Optimization of Latches and Clock Networks
133(16)
9.1 Introduction
133(2)
9.2 Background
135(2)
9.3 Disruptive Changes in Physical Synthesis
137(2)
9.4 A Graceful Physical-Synthesis Flow
139(4)
9.5 Empirical Validation
143(4)
9.6 Conclusions
147(2)
References
148(1)
10 Conclusions
149
10.1 Summary of Results
149(4)
10.2 Opportunities for Further Optimizations
153
References
155
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