Foreword |
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xi | |
About the Authors |
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xiii | |
Preface |
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xv | |
Acknowledgments |
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xvii | |
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1 | (1) |
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1.2 Power Electronics as a Technology |
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1 | (5) |
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1.3 Concept of States: Example of an Inverter |
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6 | (4) |
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10 | (3) |
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13 | (3) |
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16 | (2) |
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1.7 Power Switch Requirements |
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18 | (2) |
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20 | (1) |
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20 | (1) |
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2 Basics of Multilevel Inverters |
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21 | (2) |
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23 | (4) |
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2.2.1 Advantages of MLIs on Account of the Waveform |
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25 | (1) |
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2.2.2 Advantages of MLIs on Account of Topology |
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26 | (1) |
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2.3 Conventional Topologies |
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27 | (13) |
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2.3.1 CHB Inverter and Modulation Strategies |
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27 | (1) |
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2.3.2 Diode-Clamped Structure and Modulation Strategies |
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28 | (7) |
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2.3.3 FC Structure and Modulation Strategies |
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35 | (5) |
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2.4 Issues With Conventional Topologies |
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40 | (2) |
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42 | (1) |
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42 | (1) |
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3 Advent of New Topologies |
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43 | (1) |
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3.2 Advent of New Topologies for MLIs |
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44 | (2) |
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3.3 MLI Topologies With Reduced Device Count |
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46 | (17) |
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3.3.1 Cascaded Half-Bridge-Based Multilevel DC Link Inverter |
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47 | (1) |
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48 | (3) |
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3.3.3 Switched Series/Parallel Sources--Based MLI |
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51 | (2) |
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3.3.4 Series-Connected Switched Sources--Based MLI |
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53 | (1) |
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3.3.5 Cascaded "Bipolar Switches Cells"--Based MLI |
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54 | (1) |
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3.3.6 Packed U-Cell Topology |
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55 | (2) |
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3.3.7 Multilevel Module--Based MLI |
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57 | (1) |
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3.3.8 Reversing Voltage Topology |
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58 | (2) |
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3.3.9 Two-Switch Enabled Level Generation--Based MLI |
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60 | (3) |
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63 | (6) |
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64 | (5) |
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4 Universal Control Scheme with Voltage-Level-Based Methods |
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69 | (1) |
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4.2 Modulation Strategies for MLIs |
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70 | (8) |
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4.2.1 Multicarrier PWM with Different Carrier Signals |
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71 | (2) |
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4.2.2 Multicarrier PWM with Different Modulating Signals |
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73 | (2) |
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75 | (3) |
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4.3 Description of the UCS |
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78 | (5) |
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4.4 Implementation of UCS for a Five-Level Cascaded H-Bridge Inverter |
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83 | (5) |
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4.4.1 Simulation Model for Obtaining Aggregated Signal "a(t)" |
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84 | (2) |
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4.4.2 Simulation Model for Obtaining Actual Driving Pulses for a Five-Level Cascaded H-Bridge Inverter |
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86 | (2) |
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4.4.3 Simulation of a Five-Level Cascaded H-Bridge Inverter |
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88 | (1) |
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4.4.4 Experimental Implementation of a Five-Level Cascaded H-Bridge Inverter |
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88 | (1) |
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4.5 Implementation of UCS in Some Recently Proposed Topologies |
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88 | (16) |
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4.5.1 Implementation for 2SELG-Based MLI |
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90 | (2) |
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4.5.2 Implementation for Switched Series/Parallel Sources-Based MLI |
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92 | (4) |
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4.5.3 Implementation for Reversing Voltage Topology |
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96 | (8) |
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104 | (3) |
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104 | (3) |
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5 Multilevel Inverter Based on Bridge-Type Connected Sources |
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107 | (24) |
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107 | (1) |
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5.2 Conceptualization of Topology |
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108 | (7) |
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5.2.1 Principle of Operation |
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112 | (1) |
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112 | (2) |
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5.2.3 Voltage Across Blocking Switches |
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114 | (1) |
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5.2.4 Power Switch Configuration |
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114 | (1) |
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115 | (4) |
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5.4 Experimental Validation of Nine-Level BCS-MLI With Trinary Sources |
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119 | (1) |
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5.5 Charge Balance Control in Asymmetrically Configured BCS-MLI |
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120 | (8) |
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128 | (3) |
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129 | (2) |
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6 Cross-Connected Sources-Based Multilevel Inverter |
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131 | (1) |
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6.2 CCS-MLI Topology and Principle of Operation |
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132 | (1) |
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6.3 Mathematical Formulations for CCS-MLI |
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133 | (4) |
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6.3.1 Switching Function for Output Voltage |
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133 | (3) |
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6.3.2 Currents Through Input Sources |
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136 | (1) |
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6.3.3 Currents Through Conducting Switches |
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137 | (1) |
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6.3.4 Voltage Stress on Blocking Switches |
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137 | (1) |
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6.4 Investigations on CCS-MLI With Symmetric Source Configuration |
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137 | (14) |
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6.4.1 Optimal Switching Operation of Five-Level Inverter Based on CCS-MLI |
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138 | (2) |
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6.4.2 Equal Load Sharing Amongst the Input DC Sources in a Five-Level CCS-MLI |
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140 | (7) |
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6.4.3 Optimal Switching Operation of Higher-Level Inverters (Number of Levels > 5) Based on CCS-MLI |
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147 | (2) |
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6.4.4 Equal Load Sharing in Higher-Level Inverters (Number of Levels > 5) Based on CCS-MLI |
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149 | (2) |
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6.5 CCS-MLI With Asymmetric Source Configuration |
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151 | (6) |
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6.5.1 Asymmetric Configuration for CCS-MLI |
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154 | (3) |
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6.6 Cascaded Multilevel Inverter Using Series Connection of Cross-Connected Sources-Based Submultilevel Inverters |
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157 | (1) |
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6.7 Cascaded Multilevel Inverter With Symmetric Sources |
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158 | (10) |
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159 | (1) |
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160 | (1) |
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6.7.3 Experimental Verification |
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161 | (7) |
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6.8 Cascaded Multilevel Inverter With Asymmetric Sources |
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168 | (9) |
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169 | (1) |
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170 | (4) |
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6.8.3 Experimental Verification |
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174 | (3) |
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177 | (4) |
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178 | (3) |
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7 Comparison of Multilevel Inverter Topologies |
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181 | (15) |
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7.1.1 Comparison With Classical Topologies |
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182 | (2) |
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7.1.2 Comparison With Reduced Device Count (RDC) Topologies |
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184 | (12) |
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196 | (9) |
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204 | (1) |
Index |
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205 | |