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E-raamat: Multiple-Base Number System: Theory and Applications

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(University of Calgary, Alberta, Canada), (University of Calgary, Alberta, Canada), (University of Windsor, Ontario, Canada)
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Multiple-Base Number System: Theory and ApplicationsSuurem pilt
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"FORWARD This is a book about a new number representation that has interesting properties for special applications. It is appropriately catalogued in the area of Computer Arithmetic, which, as the name suggests, is about arithmetic that is appropriate for implementing on calculating machines. These 'machines' have changed over the millennia that humans have been building aids to performing arithmetic calculations. At the present time, arithmetic processors are buried in the architectural structures of computer processors, built mostly out of silicon, with a minimum lateral component spacing of the order of a few tens of nanometers, and vertical spacing down to just a few atoms. Arithmetic is one of the fields that even young children know and learn about. Counting with the natural numbers ( ) leads to learning to add and multiply. Negative numbers and the concept of zero lead to expanding the natural numbers to the integers ( ), and learning about division leads to fractions and the rational numbers. When we perform arithmetic "long hand" we use a positional number representation with a radix of 10; undoubtedly developed from the fact that humans have a total of 10 digits on their two hands. Early mechanical, as well as some electronic digital computers,maintained the radix of 10, but the 2-state nature of digital logic gates and storage technology leads to a radix of 2 as being more natural for electronic machines. Binary number representations, which use a fixed radix of 2, are ubiquitous in the fieldof computer arithmetic, and there are many valuable text books that cover the special arithmetic hardware circuits and processing blocks that make use of binary representations"--

"This book introduces the technique of computing with a recently introduced number representation and its arithmetic operations, referred to as the Multiple Base Number System (MBNS). The text introduces the technique and reviews the latest research in the field. The authors take the reader through an initial introduction to number representations and arithmetic in order to lay the groundwork for introducing the MBNS. They also deal with implementation issues of MBNS arithmetic processors targeted to selected applications in DSP and cryptography"--



Preface xiii
About the Authors xv
1 Technology, Applications, and Computation
1(30)
1.1 Introduction
1(1)
1.2 Ancient Roots
1(2)
1.2.1 An Ancient Binary A/D Converter
1(1)
1.2.2 Ancient Computational Aids
2(1)
1.3 Analog or Digital?
3(5)
1.3.1 An Analog Computer Fourier Analysis Tide Predictor
4(1)
1.3.2 Babbage's Difference Engine
5(1)
1.3.3 Pros and Cons
5(1)
1.3.4 The Slide Rule: An Analog Logarithmic Processor
6(2)
1.4 Where Are We Now?
8(3)
1.4.1 Moore's Law
9(1)
1.4.2 The Microprocessor and Microcontroller
9(1)
1.4.3 Advances in Integrated Circuit Technology
10(1)
1.5 Arithmetic and DSP
11(4)
1.5.1 Data Stream Processing
11(1)
1.5.2 Sampling and Conversion
12(2)
1.5.3 Digital Filtering
14(1)
1.6 Discrete Fourier Transform (DFT)
15(4)
1.6.1 Fast Fourier Transform (FFT)
17(2)
1.7 Arithmetic Considerations
19(4)
1.7.1 Arithmetic Errors in DSP
19(4)
1.8 Convolution Filtering with Exact Arithmetic
23(4)
1.8.1 Number Theoretic Transforms (NTTs)
23(1)
1.8.2 An NTT Example
24(1)
1.8.3 Connections to Binary Arithmetic
25(2)
1.9 Summary
27(1)
References
28(3)
2 The Double-Base Number System (DBNS)
31(22)
2.1 Introduction
31(1)
2.2 Motivation
32(1)
2.3 The Double-Base Number System
32(3)
2.3.1 The Original Unsigned Digit DBNS
32(1)
2.3.2 Unsigned Digit DBNS Tabular Form
33(1)
2.3.3 The General Signed Digit DBNS
34(1)
2.3.4 Some Numerical Facts
34(1)
2.4 The Greedy Algorithm
35(4)
2.4.1 Details of the Greedy Algorithm
36(2)
2.4.2 Features of the Greedy Algorithm
38(1)
2.5 Reduction Rules in the DBNS
39(5)
2.5.1 Basic Reduction Rules
39(1)
2.5.2 Applying the Basic Reduction Rules
40(2)
2.5.3 Generalized Reduction
42(2)
2.6 A Two-Dimensional Index Calculus
44(5)
2.6.1 Logarithmic Number Systems
44(1)
2.6.2 A Filter Design Study
45(2)
2.6.3 A Double-Base Index Calculus
47(2)
2.7 Summary
49(1)
References
50(3)
3 Implementing DBNS Arithmetic
53(32)
3.1 Introduction
53(2)
3.1.1 A Low-Noise Motivation
54(1)
3.2 Arithmetic Operations in the DBNS
55(5)
3.2.1 DBNR Addition
55(3)
3.2.2 DBNS Multiplication
58(2)
3.2.3 Constant Multipliers
60(1)
3.3 Conversion between Binary and DBNS Using Symbolic Substitution
60(2)
3.4 Analog Implementation Using Cellular Neural Networks
62(19)
3.4.1 Why CNNs?
62(2)
3.4.2 The Systolic Array Approach
64(1)
3.4.3 System Level Issues
64(1)
3.4.4 CNN Basics
65(1)
3.4.5 CNN Operation
66(1)
3.4.6 Block and Circuit Level Descriptions of the CNN Cell
67(2)
3.4.7 DBNS Addition CNN Templates Using Overlay and Row Reduction Rules
69(1)
3.4.8 Designing the Templates
70(2)
3.4.9 Handling Interference between Cells
72(2)
3.4.10 CMOS Implementation of DBNS CNN Reduction Rules
74(3)
3.4.11 A Complete CNN Adder Cell
77(2)
3.4.12 Avoiding Feedback Races
79(2)
3.5 Summary
81(1)
References
82(3)
4 Multiplier Design Based on DBNS
85(24)
4.1 Introduction
85(1)
4.1.1 A Brief Background
85(1)
4.1.2 Extremely Large Numbers
86(1)
4.2 Multiplication by a Constant Multiplier
86(1)
4.3 Using the DBNS
87(3)
4.4 DBNS Multiplication with Subquadratic Complexity
90(2)
4.5 General Multiplier Structure
92(8)
4.6 Results and Comparisons
100(1)
4.7 Some Multiplier Designs
101(3)
4.7.1 180 nm CMOS Technology
101(2)
4.7.2 FPGA Implementation
103(1)
4.8 Example Applications
104(1)
4.9 Summary
105(1)
References
105(4)
5 The Multidimensional Logarithmic Number System (MDLNS)
109(26)
5.1 Introduction
109(1)
5.2 The Multidimensional Logarithmic Number System (MDLNS)
109(1)
5.3 Arithmetic Implementation in the MDLNS
110(6)
5.3.1 Multiplication and Division
111(1)
5.3.2 Addition and Subtraction
111(1)
5.3.4 Approximations to Unity
112(4)
5.4 Multiple-Digit MDLNS
116(5)
5.4.1 Error-Free Integer Representations
116(4)
5.4.2 Non-Error-Free Integer Representations
120(1)
5.5 Half-Domain MDLNS Filter
121(10)
5.5.1 Inner Product Step Processor
121(2)
5.5.2 Single-Digit 2DLNS Computational Unit
123(5)
5.5.3 Extending to Multiple Bases
128(1)
5.5.4 Extending to Multiple Digits
129(1)
5.5.5 General Binary-to-MDLNS Conversion
130(1)
5.6 Summary
131(1)
References
132(3)
6 Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion
135(34)
6.1 Introduction
135(1)
6.2 Single-Digit 2DLNS Conversion
136(5)
6.2.1 Single-Digit 2DLNS-to-Binary Conversion
136(2)
6.2.2 Binary-to-Single-Digit 2DLNS Conversion
138(3)
6.3 Range-Addressable Lookup Table (RALUT)
141(4)
6.3.1 RALUT Architecture
141(3)
6.3.1.1 Binary-to-Single-Digit 2DLNS Structure
144(1)
6.4 Two-Digit 2DLNS-to-Binary Conversion
145(1)
6.4.1 Two-Digit 2DLNS-to-Binary Conversion Architecture
145(1)
6.5 Binary-to-Two-Digit 2DLNS Conversion
145(12)
6.5.1 Binary-to-Two-Digit 2DLNS Conversion (Quick Method)
147(2)
6.5.1.1 Quick Binary-to-Two-Digit 2DLNS Conversion Architecture
149(1)
6.5.2 Binary-to-Two-Digit 2DLNS Conversion (High/Low Method)
149(2)
6.5.2.1 Modifying the RALUT for the High/Low Approximation
151(1)
6.5.2.2 High/Low Binary-to-Two-Digit 2DLNS Architecture
152(1)
6.5.3 Binary-to-Two-Digit 2DLNS Conversion (Brute-Force Method)
152(3)
6.5.3.1 Brute-Force Conversion Architecture
155(1)
6.5.4 Binary-to-Two-Digit 2DLNS Conversion (Extended-Brute-Force Method)
156(1)
6.5.5 Comparison of Binary-to-Two-Digit 2DLNS Conversion Methods
156(1)
6.6 Multidigit 2DLNS Representation (n >2)
157(1)
6.6.1 Multidigit 2DLNS-to-Binary Conversion
157(1)
6.6.2 Binary-to-Multidigit 2DLNS Conversion (Quick Method)
157(1)
6.6.3 Binary-to-Multidigit 2DLNS Conversion (High/Low Method)
157(1)
6.6.4 Binary-to-Multidigit 2DLNS Conversion (Brute-Force Method)
158(1)
6.7 Extending to More Bases
158(1)
6.8 Physical Implementation
159(1)
6.9 Very Large-Bit Word Binary-to-DBNS Converter
160(6)
6.9.1 Conversion Methods for Large Binary Numbers
161(2)
6.9.2 Reducing the Address Decode Complexity
163(1)
6.9.3 Results and Discussion
163(3)
6.10 Summary
166(1)
References
166(3)
7 Multidimensional Logarithmic Number System: Addition and Subtraction
169(34)
7.1 Introduction
169(1)
7.2 MDLNS Representation
170(1)
7.2.1 Simplified MDLNS Representation
170(1)
7.3 Simple Single-Digit MDLNS Addition and Subtraction
171(1)
7.4 Classical Method
172(3)
7.4.1 LNS Implementation
173(1)
7.4.2 MDLNS Implementation
173(2)
7.5 Single-Base Domain
175(5)
7.5.1 Single-Digit MDLNS to Single-Base Domain
176(2)
7.5.2 Single-Base Domain to Single-Digit MDLNS
178(2)
7.5.3 MDLNS Magnitude Comparison
180(1)
7.6 Addition in the Single-Base Domain
180(8)
7.6.1 Computing the Addition Table
180(1)
7.6.1.1 Minimizing the Search Space
181(2)
7.6.1.2 Table Redundancy
183(1)
7.6.1.3 RALUT Implementation
183(1)
7.6.1.4 Table Merging
183(3)
7.6.1.5 Alternatives for m
186(1)
7.6.2 The Complete Structure
187(1)
7.6.3 Results
187(1)
7.7 Subtraction in the Single-Base Domain
188(5)
7.7.1 Computing the Subtraction Table
188(1)
7.7.1.1 Minimizing the Search Space
189(1)
7.7.1.2 RALUT Implementation and Table Reduction
190(2)
7.7.2 The Complete Structure
192(1)
7.7.3 Results
192(1)
7.8 Single-Digit MDLNS Addition/Subtraction
193(1)
7.8.1 The Complete Structure
193(1)
7.8.2 Results
193(1)
7.9 Two-Digit MDLNS Addition/Subtraction
194(1)
7.10 MDLNS Addition/Subtraction with Quantization Error Recovery
195(3)
7.10.1 Feedback Accumulation in SBD
196(1)
7.10.2 Feedback Accumulation in SBD (with Full SBD Range)
197(1)
7.10.3 Increasing the SBD Accuracy Internally
197(1)
7.11 Comparison to an LNS Case
198(3)
7.11.1 Addition
199(1)
7.11.2 Subtraction
199(1)
7.11.3 Comparisons
200(1)
7.12 Summary
201(1)
References
201(2)
8 Optimizing MDLNS Implementations
203(24)
8.1 Introduction
203(1)
8.2 Background
203(2)
8.2.1 Single-Digit 2DLNS Representation
203(1)
8.2.2 Single-Digit 2DLNS Inner Product Computational Unit
204(1)
8.3 Selecting an Optimal Base
205(3)
8.3.1 The Impact of the Second Base on Hardware Cost
205(1)
8.3.2 Defining a Finite Limit for the Second Base
206(1)
8.3.3 Finding the Optimal Second Base
207(1)
8.3.3.1 Algorithmic Search
207(1)
8.3.3.2 Range Search
208(1)
8.3.3.3 Fine Adjustment
208(1)
8.4 One-Bit Sign Architecture
208(3)
8.4.1 Representation Efficiency
209(1)
8.4.2 Effects on Determining the Optimal Base
209(1)
8.4.3 Effects on Hardware Architecture
209(2)
8.5 Example Finite Impulse Response Filter
211(12)
8.5.1 Optimizing the Base through Analysis of the Coefficients
214(1)
8.5.1.1 Single-Digit Coefficients
214(1)
8.5.1.2 Two-Digit Coefficients
215(1)
8.5.1.3 Comparison of Single- and Two-Digit Coefficients
216(1)
8.5.1.4 Effects on the Two-Digit Data
216(1)
8.5.2 Optimizing the Base through Analysis of the Data
217(1)
8.5.3 Optimizing the Base through Analysis of Both the Coefficients and Data
218(1)
8.5.3.1 Single-Digit Coefficients and Two-Digit Data
219(1)
8.5.3.2 Comparison to the Individual Optimal Base
219(1)
8.5.3.3 Two-Digit Coefficients and Two-Digit Data
220(1)
8.5.3.4 Comparison to the Individual Optimal Base
220(1)
8.5.4 Comparison of Base 3 to the Optimal Bases
220(1)
8.5.5 Comparison to General Number Systems
221(2)
8.6 Extending the Optimal Base to Three Bases
223(1)
8.7 Summary
224(1)
References
225(2)
9 Integrated Circuit Implementations and RALUT Circuit Optimizations
227(20)
9.1 Introduction
227(1)
9.2 A 15th-Order Single-Digit Hybrid DBNS Finite Impulse Response (FIR) Filter
227(2)
9.2.1 Architecture
228(1)
9.2.2 Specifications
228(1)
9.2.3 Results
229(1)
9.3 A 53rd-Order Two-Digit DBNS FIR Filter
229(2)
9.3.1 Specifications for the Two-Digit 2DLNS Filter
230(1)
9.3.2 Results
231(1)
9.4 A 73rd-Order Low-Power Two-Digit MDLNS Eight-Channel Filterbank
231(2)
9.4.1 Specifications
232(1)
9.4.2 Results
232(1)
9.4.3 Improvements
232(1)
9.4.4 Results
233(1)
9.5 Optimized 75th-Order Low-Power Two-Digit MDLNS Eight-Channel Filterbank
233(2)
9.5.1 Results
234(1)
9.6 A RISC-Based CPU with 2DLNS Signal Processing Extensions
235(2)
9.6.1 Architecture and Specifications
235(1)
9.6.2 Results
236(1)
9.7 A Dynamic Address Decode Circuit for Implementing Range Addressable Look-Up Tables
237(7)
9.7.1 Efficient RALUT Implementation
237(1)
9.7.2 Dynamic Address Decoders (LUT)
238(2)
9.7.3 Dynamic Range Address Decoders (RALUT)
240(2)
9.7.4 Full Custom Implementation
242(1)
9.7.5 Comparison with Past Designs
243(1)
9.7.6 Additional Optimizations
243(1)
9.8 Summary
244(1)
References
244(3)
10 Exponentiation Using Binary-Fermat Number Representations
247(20)
10.1 Introduction
247(2)
10.1.1 Some Examples of Exponentiation Techniques
247(1)
10.1.2 About This
Chapter
248(1)
10.2 Theoretical Background
249(3)
10.3 Finding Suitable Exponents
252(2)
10.3.1 Bases 2 and 3
253(1)
10.4 Algorithm for Exponentiation with a Low Number of Regular Multiplications
254(3)
10.5 Complexity Analysis Using Exponential Diophantine Equations
257(3)
10.6 Experiments with Random Numbers
260(2)
10.6.1 Other Bases
261(1)
10.7 A Comparison Analysis
262(1)
10.8 Final Comments
262(1)
10.9 Summary
263(1)
References
263(4)
Index 267
Vassil S. Dimitrov earned a Ph.D degree in applied mathematics from the Bulgarian Academy of Sciences in 1995. Since 1995, he has held postdoctoral positions at the University of Windsor, Ontario (19961998) and Helsinki University of Technology (19992000). From 1998 to 1999, he worked as a research scientist for Cigital, Dulles, Virginia (formerly known as Reliable Software Technology), where he conducted research on different cryptanalysis problems. Since 2001, he has been an associate professor in the Department of Electrical and Computer Engineering, Schulich School of Engineering, University of Calgary, Alberta. His main research areas include implementation of cryptographic protocols, number theoretic algorithms, computational complexity, image processing and compression, and related topics.

Graham Jullien recently retired as the iCORE chair in Advanced Technology Information Processing Systems, and the director of the ATIPS Laboratories, in the Department of Electrical and Computer Engineering, Schulich School of Engineering, at the University of Calgary. His long-term research interests are in the areas of integrated circuits (including SoC), VLSI signal processing, computer arithmetic, high-performance parallel architectures, and number theoretic techniques. Since taking up his chair position at Calgary, he expanded his research interests to include security systems, nanoelectronic technologies, and biomedical systems. He was also instrumental, along with his colleagues, in developing an integration laboratory cluster to explore next-generation integrated microsystems. Dr. Jullien is a fellow of the Royal Society of Canada, a life fellow of the IEEE, a fellow of the Engineering Institute of Canada, and until recently, was a member of the boards of directors of DALSA Corp., CMC Microsystems, and Micronet R&D. He has published more than 400 papers in refereed technical journals and conference proceedings, and has served on the organizing and program committees of many international conferences and workshops over the past 35 years. Most recently he was the general chair for the IEEE International Symposium on Computer Arithmetic in Montpellier in 2007, and was guest coeditor of the IEEE Proceedings special issue System-on-Chip: Integration and Packaging, June 2006.

Roberto Muscedere received his BASc degree in 1996, MASc degree in 1999, and Ph.D in 2003, all from the University of Windsor in electrical engineering. During this time he also managed the microelectronics computing environment at the Research Centre for Integrated Microsystems (formally the VLSI Research Group) at the University of Windsor. He is currently an associate professor in the Electrical and Computer Engineering Department at the University of Windsor. His research areas include the implementation of high-performance and low-power VLSI circuits, full and semicustom VLSI design, computer arithmetic, HDL synthesis, digital signal processing, and embedded systems. Dr. Muscedere has been a member of the IEEE since 1994.
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