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E-raamat: Nano-CMOS and Post-CMOS Electronics: Circuits and design, Volume 2

Edited by (Louisiana State University, Division of Electrical & Computer Engineering, Baton Rouge, USA), Edited by (University of North Texas, Department of Computer Science and Engineering, USA)
  • Formaat: EPUB+DRM
  • Sari: Materials, Circuits and Devices
  • Ilmumisaeg: 05-May-2016
  • Kirjastus: Institution of Engineering and Technology
  • Keel: eng
  • ISBN-13: 9781785610004
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Nano-CMOS and Post-CMOS Electronics: Circuits and design, Volume 2Suurem pilt
  • Formaat: EPUB+DRM
  • Sari: Materials, Circuits and Devices
  • Ilmumisaeg: 05-May-2016
  • Kirjastus: Institution of Engineering and Technology
  • Keel: eng
  • ISBN-13: 9781785610004
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The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the circuit and systems levels including modelling and design approaches and issues.



Topics covered include self-healing analog and radio frequency circuits; on-chip gate delay variability measurement in scaled technology node; nanoscale finFET devices for PVT aware SRAM; data stability and write ability enhancement techniques for finFET SRAM circuits; low-leakage techniques for nanoscale CMOS circuits; thermal effects in carbon nanotube VLSI interconnects; lumped electro-thermal modeling and analysis of carbon nanotube interconnects; high-level synthesis of digital integrated circuits in the nanoscale mobile electronics era; SPICEless RTL design optimization of nanoelectronic digital integrated circuits; green on-chip inductors for three-dimensional integrated circuits; 3D network-on-chips; and DNA computing.



This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
Preface xiii
1 Self-healing analog/RF circuits 1(34)
1.1 Introduction
1(2)
1.2 Indirect performance sensing
3(1)
1.3 Pre-silicon indirect sensor modeling via SR
4(7)
1.3.1 L0-norm regularization
5(2)
1.3.2 L1-norm regularization
7(2)
1.3.3 Accuracy of L1-norm regularization
9(2)
1.4 Post-silicon indirect sensor calibration via Bayesian model fusion
11(6)
1.4.1 Prior knowledge definition
12(2)
1.4.2 MAP estimation
14(3)
1.5 On-chip self-healing flow
17(3)
1.6 Case study
20(12)
1.6.1 25 GHz differential Colpitts VCO
20(6)
1.6.2 60 GHz LNA
26(6)
1.7 Conclusion
32(1)
References
32(3)
2 On-chip gate delay variability measurement in scaled technology node 35(36)
2.1 Introduction
35(1)
2.2 Classification of variability
36(2)
2.3 Sources of variability
38(1)
2.3.1 Random dopant fluctuations
38(1)
2.3.2 Line edge roughness
38(1)
2.3.3 Oxide thickness variation
39(1)
2.4 Related work on variability measurement
39(3)
2.4.1 Gate delay variability
39(2)
2.4.2 Rise and fall gate delay variability
41(1)
2.5 Gate delay measurement using reconfigurable ring oscillator
42(14)
2.5.1 Gate delay measurement cell
42(1)
2.5.2 Reconfigurable ring oscillator structure
43(5)
2.5.3 Measured results
48(1)
2.5.4 Poly-pitch effect
49(2)
2.5.5 Length of diffusion effect
51(1)
2.5.6 Delay variation due to layout orientation
52(1)
2.5.7 Delay variation due to supply voltage
52(1)
2.5.8 Measured accuracy of the delay measurement
53(2)
2.5.9 Comparison with other works
55(1)
2.6 Measurement of rise and fall delays using standard RO
56(1)
2.7 Rise and fall gate delay measurement using RRO
57(4)
2.7.1 Gate delay measurement cell
57(1)
2.7.2 Rise and fall delays of non-inverting gate
58(2)
2.7.3 Rise and fall delays of inverting gate
60(1)
2.8 Test chip and measurement results
61(1)
2.8.1 Measurement of duty cycle
61(1)
2.9 Measured results
62(4)
2.9.1 Impact of body-bias
63(2)
2.9.2 Impact of supply voltage
65(1)
2.9.3 Measurement accuracy
65(1)
2.9.4 Comparison with the existing techniques
65(1)
2.10 Summary and conclusions
66(1)
References
67(4)
3 Nanoscale FinFET devices for PVT-aware SRAM 71(42)
3.1 Introduction
71(1)
3.2 Nanoscale FinFET devices
72(7)
3.2.1 Bulk FinFET
73(2)
3.2.2 SOI FinFET
75(4)
3.3 FinFET-based SRAM topologies
79(12)
3.3.1 IG-FinFET-based 6T SRAM
80(2)
3.3.2 Back-gate bias IG-FinFET-based 6T SRAM
82(1)
3.3.3 IG-FinFET-based PPN 10T SRAM
83(5)
3.3.4 Stability analysis
88(3)
3.4 FinFET-based SRAM design challenges
91(1)
3.5 PVT-aware SRAM design
92(14)
3.5.1 PVT mitigation techniques
93(2)
3.5.2 PVT-aware SRAM designs
95(8)
3.5.3 Stability analysis
103(3)
3.6 Conclusion
106(1)
References
106(7)
4 Data stability and write ability enhancement techniques for FinFET SRAM circuits 113(28)
4.1 Introduction
113(1)
4.2 Six-FinFET SRAM cells
114(13)
4.2.1 Conventional six-FinFET SRAM cell
114(2)
4.2.2 Independent-gate FinFET SRAM cell
116(1)
4.2.3 SRAM cell with asymmetrically overlap/underlap engineered FinFETs
117(3)
4.2.4 Hybrid SRAM cell with asymmetrically overlapped/underlapped bitline access transistors
120(1)
4.2.5 SRAM cell with asymmetrically gate-underlapped transistors
121(4)
4.2.6 Single-ended read SRAM cell with underlap engineered symmetrical-FinFETs
125(2)
4.3 Fabrication and SRAM cell area comparison
127(1)
4.4 Case study: 8KBit memory arrays designed with different SRAM cells
128(5)
4.4.1 Read static noise margin
128(1)
4.4.2 Hold static noise margin
129(1)
4.4.3 Write voltage margin
130(1)
4.4.4 Data access speed
131(1)
4.4.5 Leakage power consumption
132(1)
4.5 Variations of underlap (overlap) lengths due to process imperfections
133(5)
4.6 Conclusions
138(1)
References
138(3)
5 Low-leakage techniques for nanoscale CMOS circuits 141(32)
5.1 Introduction
141(1)
5.2 Device scaling
142(3)
5.2.1 Constant voltage scaling
144(1)
5.2.2 Constant field scaling
144(1)
5.2.3 Generalized scaling
145(1)
5.3 Power dissipation
145(3)
5.3.1 Leakage power dissipation
145(1)
5.3.2 Leakage current components
146(2)
5.4 Issue of leakage current
148(1)
5.5 Variability issues and aware design
148(2)
5.6 Leakage reduction techniques
150(12)
5.6.1 MTCMOS technique
150(2)
5.6.2 Forced stack technique
152(2)
5.6.3 Dual threshold CMOS (DTCMOS) technique
154(1)
5.6.4 SCCMOS (super cut-off CMOS) technique
154(2)
5.6.5 Leakage feedback technique
156(1)
5.6.6 Variable threshold CMOS (VTCMOS) technique
157(1)
5.6.7 LECTOR technique
158(1)
5.6.8 Sleepy stack technique
158(1)
5.6.9 Sleepy keeper technique
159(1)
5.6.10 VCLEARIT technique
160(1)
5.6.11 GALEOR technique
161(1)
5.7 Leakage analysis
162(5)
5.8 Conclusion
167(1)
References
167(6)
6 Thermal effects in carbon nanotube VLSI interconnects 173(28)
6.1 Introduction
173(1)
6.2 Present status of VLSI interconnect
174(1)
6.3 Survey of CNT-based interconnects
175(1)
6.4 Electrical properties
176(9)
6.4.1 Equivalent resistance (Reqv)
177(3)
6.4.2 Equivalent inductance (Leqv)
180(1)
6.4.3 Equivalent capacitance (Ceqv)
181(1)
6.4.4 Effective mean free path (λeff)
182(2)
6.4.5 Equivalent circuit
184(1)
6.5 Thermal properties
185(11)
6.5.1 Thermal properties of SWCNTs
185(2)
6.5.2 Thermal properties of SWCNT bundle
187(2)
6.5.3 Thermal properties of MWCNT
189(1)
6.5.4 Iterative scheme for R and T
190(1)
6.5.5 Temperature profiling inside the interconnect
191(2)
6.5.6 Performances in terms of S-parameters
193(3)
6.6 Conclusion
196(1)
References
196(5)
7 Lumped electro-thermal modeling and analysis of carbon nanotube interconnects 201(18)
7.1 Introduction
201(1)
7.2 Electrical modeling of CNTs
202(3)
7.3 Thermal modeling for CNTs
205(11)
7.4 Conclusion
216(1)
References
217(2)
8 High-level synthesis of digital integrated circuits in the nanoscale mobile electronics era 219(48)
8.1 Introduction
219(3)
8.2 Fundamentals on high level synthesis
222(7)
8.2.1 Overview on HLS design process
222(2)
8.2.2 Need for HLS
224(1)
8.2.3 Scheduling algorithms
225(3)
8.2.4 Allocation and binding
228(1)
8.3 Power, energy, or leakage aware HLS for nanoscale ICs
229(12)
8.3.1 Selected power, energy, or leakage aware HLS methods
229(4)
8.3.2 Effects of loop manipulation on power and delay of the design
233(6)
8.3.3 Other design space exploration approaches during HLS
239(2)
8.4 Bio/nature-inspired algorithms for DSE framework
241(11)
8.4.1 Selected bio/nature-inspired approaches
241(2)
8.4.2 A BFOA-exploration process
243(1)
8.4.3 Encoding/initialization of the datapath bacterium
244(1)
8.4.4 Encoding of the auxiliary bacterium
245(1)
8.4.5 Proposed movement of bacterium
246(2)
8.4.6 Models for metric
248(1)
8.4.7 Results of the BFOA-exploration process
248(4)
8.5 HLS approaches for secure information processing
252(6)
8.5.1 Related work
252(1)
8.5.2 Exploration process of hardware Trojan secured datapath: security against untrusted third party digital IPs
253(5)
8.5.3 Results of exploration process of hardware Trojan secured datapath
258(1)
8.6 Selected tools available for HLS
258(2)
8.6.1 Selected commercial tools for HLS
259(1)
8.6.2 Selected free HLS tools
260(1)
8.7 Conclusion and future directions of HLS
260(1)
References
261(6)
9 SPICEless RTL design optimization of nanoelectronic digital integrated circuits 267(38)
9.1 Introduction
267(4)
9.2 The concept of SPICEless RTL optimization during HLS
271(1)
9.3 The issues in RTL optimization of power dissipation in digital circuits
272(2)
9.4 Power optimization at RTL: state-of-the-art
274(4)
9.4.1 Existing methods for RTL power optimization
274(2)
9.4.2 Multiple oxide thickness technology for gate-oxide leakage optimization
276(2)
9.5 A specific SPICEless RTL optimization approach
278(7)
9.5.1 The overall RTL optimization flow
278(1)
9.5.2 Objective function for RTL optimization
279(2)
9.5.3 A specific heuristic algorithm for RTL optimization
281(4)
9.6 SPICEless characterization of the RTL component library
285(8)
9.6.1 Gate-oxide leakage modeling
287(2)
9.6.2 Propagation delay modeling
289(2)
9.6.3 Analytical modeling of RTL components
291(2)
9.7 Experimental results for the specific RTL optimization
293(5)
9.8 Conclusions and future directions of research
298(1)
Acknowledgments
299(1)
References
299(6)
10 Green on-chip inductors for three-dimensional integrated circuits: concepts, algorithms and applications 305(32)
10.1 Introduction
305(2)
10.2 Effect of various parameters of an on-chip inductor
307(9)
10.2.1 Impact of process parameters
309(4)
10.2.2 Design parameters
313(3)
10.3 Low-frequency applications
316(10)
10.3.1 DC—DC converter design
316(7)
10.3.2 Resonant clocking implementation
323(3)
10.4 Micro-channel shielding
326(8)
10.5 Summary and conclusions
334(1)
References
334(3)
11 3D NoC: a promising alternative for tomorrow's nanosystem design 337(42)
11.1 Introduction
337(3)
11.1.1 NoC basics
338(1)
11.1.2 Transition towards 3D
338(2)
11.2 Design challenges in 3D NoC
340(7)
11.2.1 Design challenges
341(1)
11.2.2 Macro-architecture
341(4)
11.2.3 Emerging technological challenges
345(2)
11.3 Performance centric design of 3D NoCs
347(2)
11.3.1 Interconnection topology development
347(1)
11.3.2 Routing policy
347(2)
11.3.3 Flow control mechanism
349(1)
11.4 Architectural optimization of 3D NoCs
349(3)
11.4.1 Router architecture
349(1)
11.4.2 Network interface controller
350(1)
11.4.3 Interconnection
351(1)
11.4.4 Memory
352(1)
11.5 Thermal-aware design
352(1)
11.6 Photonic 3D NoC
353(5)
11.6.1 Photonic interconnect for manycore ICs
353(4)
11.6.2 Multi-dimensional design issues in 3D PNoC
357(1)
11.7 Wireless 3D NoC
358(3)
11.7.1 Low-latency-based wireless 3D NoCs
358(1)
11.7.2 Inductive coupling interconnected application-specific 3D NoC
359(1)
11.7.3 Reconfigurable hybrid 3D wireless NoC
360(1)
11.8 3D NoC simulators
361(3)
11.8.1 NoC simulation
361(3)
11.9 Reliability and fault tolerance in 3D NoCs
364(2)
11.10 Conclusion
366(1)
References
366(13)
12 A new paradigm towards performance centric computation beyond CMOS: DNA computing 379(30)
12.1 Introduction
379(8)
12.1.1 DNA structure
380(1)
12.1.2 Operations on DNA solutions
381(5)
12.1.3 How DNA computers work? Power of DNA computer
386(1)
12.1.4 History of DNA computing
386(1)
12.2 DNA computing models
387(10)
12.2.1 Adleman—Lipton model
388(5)
12.2.2 Sticker model
393(4)
12.3 Performing arithmetic and logic operations using DNA
397(5)
12.3.1 AND operation
398(1)
12.3.2 OR operation
399(1)
12.3.3 XOR operation
400(1)
12.3.4 NOT operation
400(1)
12.3.5 Comparator
400(2)
12.4 Implementing data structures using DNA
402(3)
12.4.1 Stack and queue using DNA
402(1)
12.4.2 List using DNA
403(1)
12.4.3 Map using DNA
404(1)
12.5 Conclusion
405(1)
References
405(4)
Index 409
Saraju Mohanty is Professor at the Department of Computer Science and Engineering, University of North Texas, where he is the director of NanoSystem Design Laboratory (NSDL). His research interests focus on Energy-Efficient High-Performance Secure Electronic Systems. He is the author of more than 200 peer-reviewed journal and conference publications and 3 books. Prof. Mohanty is the current Chair of Technical Committee on Very Large Scale Integration (TCVLSI) of the IEEE Computer Society, is on the editorial board of IET Circuits, Devices and Systems, Integration and Journal of Low Power Electronics, and serves on the organizing and program committee of several international conferences.



Ashok Srivastava is Professor of Engineering at the Division of Electrical & Computer Engineering of Louisiana State University, Baton Rouge, where his research interests lie in low-power VLSI design and testability for nanoscale transistors and integration, and nanoelectronics with focus on novel emerging devices and integrated circuit design based on carbon nanotubes, graphene and other reduced dimension 2D materials. He is the author of more than 160 technical papers including conference proceedings, book chapters, a patent and a book on Carbon Based Electronics. Prof. Srivastava serves on the Editorial Review Board of Modeling and Numerical Simulation of Material Science (MNSMS), Journal of Material Science and Chemical Engineering (JMSCE), The Scientific World Journal (Electronics) and is Editor-in-Chief of the Journal of Sensor Technology.
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