Muutke küpsiste eelistusi

E-raamat: Nanometer Frequency Synthesis Beyond the Phase-Locked Loop

(Texas Instruments Incorporated)
Teised raamatud teemal:
  • Formaat - EPUB+DRM
  • Hind: 146,90 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
  • Raamatukogudele
Nanometer Frequency Synthesis Beyond the Phase-Locked LoopSuurem pilt
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

The chief clock architect at a microelectronics company, Xiu draws on number theory and Fourier analysis to investigate how to improve the relationship between time and number in very large integrated circuits. In particular, he asks whether it is possible to represent information with time--a transistor's rate of switching--as well as with level of voltage or current, as is now the case. He covers clock signal in electronic systems, existing frequency synthesis techniques, time-average-frequency, flying-adder direct period synthesis architecture, digital-to-frequency converter, the new frontier in electronic system design, and the future era of time. Annotation ©2012 Book News, Inc., Portland, OR (booknews.com)

Introducing a new, pioneering approach to integrated circuit design

Nanometer Frequency Synthesis Beyond Phase-Locked Loop introduces an innovative new way of looking at frequency that promises to open new frontiers in modern integrated circuit (IC) design. While most books on frequency synthesis deal with the phase-locked loop (PLL), this book focuses on the clock signal. It revisits the concept of frequency, solves longstanding problems in on-chip clock generation, and presents a new time-based information processing approach for future chip design.

Beginning with the basics, the book explains how clock signal is used in electronic applications and outlines the shortcomings of conventional frequency synthesis techniques for dealing with clock generation problems. It introduces the breakthrough concept of Time-Average-Frequency, presents the Flying-Adder circuit architecture for the implementation of this approach, and reveals a new circuit device, the Digital-to-Frequency Converter (DFC). Lastly, it builds upon these three key components to explain the use of time rather than level to represent information in signal processing.

Provocative, inspiring, and chock-full of ideas for future innovations, the book features:

  • A new way of thinking about the fundamental concept of clock frequency
  • A new circuit architecture for frequency synthesis: the Flying-Adder direct period synthesis
  • A new electronic component: the Digital-to-Frequency Converter
  • A new information processing approach: time-based vs. level-based
  • Examples demonstrating the power of this technology to build better, cheaper, and faster systems

Written with the intent of showing readers how to think outside the box, Nanometer Frequency Synthesis Beyond the Phase-Locked Loop is a must-have resource for IC design engineers and researchers as well as anyone who would like to be at the forefront of modern circuit design.

Preface xi
1 Clock Signal in Electronic Systems
1(36)
1.1 The Significance of Clock Signal
1(4)
1.1.1 Clock Signal
1(2)
1.1.2 The Aim of This Book
3(2)
1.2 The Characteristics of Clock Signal
5(13)
1.2.1 Jitter and Phase Noise
5(8)
1.2.2 Clock Phase
13(2)
1.2.3 Clock Skew
15(3)
1.3 Clock Signal Driving Digital System
18(6)
1.3.1 Clock Signal as a Trigger
18(1)
1.3.2 Timing-Closure Design Constraint: The Safeguard for Reliable Operation
18(3)
1.3.3 Clock Jitter and Design Constraint
21(1)
1.3.4 Clock Skew and Design Constraint
21(3)
1.4 Clock Signal Driving Sampling System
24(6)
1.4.1 Clock Signal as a Switch
24(1)
1.4.2 Clock Signal and Analog-to-Digital Converter
25(3)
1.4.3 Clock Signal and Digital-to-Analog Converter
28(2)
1.5 Extracting Clock Signal From Data: Clock Data Recovery
30(2)
1.6 Clock Usage in System-on-Chip
32(1)
1.7 Two Fields: Clock Generation and Clock Distribution
33(4)
Bibliography
34(3)
2 Clock Generation: Existing Frequency Synthesis Techniques
37(16)
2.1 Direct Analog Frequency Synthesis
38(1)
2.2 Direct Digital Frequency Synthesis
39(2)
2.3 Indirect Method (Phase-Locked Loop Based)
41(10)
2.3.1 Brief History
41(1)
2.3.2 The Basic Structure of the Phase-Locked Loop (PLL)
42(3)
2.3.3 An Example of Third-Order Type-II Charge Pump PLL
45(2)
2.3.4 Major PLL Architectures
47(4)
2.4 The Shared Goal: All Cycles Have Same Length-in-Time
51(2)
Bibliography
51(2)
3 Time-Average-Frequency
53(12)
3.1 The Scale of Level and the Scale of Time
53(1)
3.2 What Is Frequency?
54(2)
3.2.1 How Is Frequency Implemented In Circuit Design?
55(1)
3.2.2 How Is Frequency Used in Electronic System?
55(1)
3.2.3 "Instantaneous Frequency" and "Instantaneous Period"
55(1)
3.3 Reinvestigating the Frequency Concept: the Birth of Time-Average-Frequency
56(3)
3.4 Time-Average-Frequency in Circuit Implementation
59(2)
3.5 Average Frequency, Time-Average-Frequency, and Fundamental Frequency
61(1)
3.6 The Need of a Theory
62(1)
3.7 The Summary: Why Do We Need Time-Average-Frequency?
63(2)
Bibliography
63(2)
4 Flying-Adder Direct Period Synthesis Architecture
65(102)
4.1 The Working Principle
65(3)
4.1.1 The First Structure
65(2)
4.1.2 One Step Forward
67(1)
4.2 The Major Challenges in the Flying-Adder Circuit
68(6)
4.2.1 The Glitch Problem
68(2)
4.2.2 The Speed of Accumulator
70(1)
4.2.3 The Generation of the K Inputs
70(4)
4.3 The Circuit of Proof of Concept
74(3)
4.3.1 Using Two Paths to Solve the Glitch Problem
74(1)
4.3.2 Synchronize the Two Paths
75(1)
4.3.3 Pipeline for Adder Speed
76(1)
4.4 The Working Circuitry
77(10)
4.4.1 The Proof of Glitch-Free
78(3)
4.4.2 The Order of the Input Signals
81(1)
4.4.3 The Analysis of Circuit Speed
81(1)
4.4.4 The Analysis of Power Consumption
82(1)
4.4.5 The Behavioral Simulation
82(3)
4.4.6 The Extension to Multipaths
85(2)
4.5 Frequency Transfer Function, Frequency Range, Frequency Resolution, and Frequency Switching Speed
87(1)
4.6 The Technique of Post Divider Fractional Bits Recovery
88(2)
4.6.1 Post Divider Fractional Bits Recovery (PDFR)
88(1)
4.6.2 PDFR for Virtually Boosting the Number of Inputs K
89(1)
4.6.3 The Effective Fraction after Post Divider
90(1)
4.7 Flying-Adder PLL: FAPLL
90(1)
4.8 Flying-Adder Fractional Divider
91(1)
4.9 Integer-Flying-Adder Architecture
92(6)
4.9.1 Integer-Only FAPLL: How Close Can It Reach an Integer?
92(2)
4.9.2 Incorporating Flying-Adder Fractional Divider Inside Integer-N PLL
94(1)
4.9.3 Integer-Flying-Adder Architecture
95(3)
4.10 The Algorithm to Search Optimum Parameters
98(1)
4.11 The Construction of the Accumulator
99(5)
4.12 The Construction of the High Speed Multiplex
104(3)
4.13 Non-2's Power Flying-Adder Circuit
107(2)
4.14 Expanding VCO Frequency Range in Nanometer CMOS Processes
109(1)
4.15 Multiple Flying-Adder Synthesizers
110(1)
4.16 Flying-Adder Implementation Styles
111(1)
4.17 Simulation Approaches
112(1)
4.18 The Impact of Input Mismatch on Output Jitter
113(14)
4.18.1 The Cause of Mismatch and Its Characteristics
113(3)
4.18.2 The Mismatch Modeling
116(1)
4.18.3 The Mismatch and the Frequency Control Word
117(1)
4.18.4 The Mismatch's Impact on Output Period
118(5)
4.18.5 The Mismatch's Impact on Output Spectrum
123(2)
4.18.6 Summary on Mismatch's Impact
125(2)
4.19 Flying-Adder Circuit as Digital Controlled Oscillator
127(1)
4.20 Flying-Adder Terminology
128(1)
4.21 Flying-Adder Synthesizer and Time-Average-Frequency: The Experimental Evidence
129(25)
4.21.1 The FAPLL Structure
129(3)
4.21.2 Jitter Performance
132(1)
4.21.3 Frequency Generation Capability
133(1)
4.21.4 Frequency Resolution
133(1)
4.21.5 Frequency Spectrum
133(4)
4.21.6 Instantaneous Switching Demonstration
137(1)
4.21.7 Time-Average-Frequency Demonstration
137(7)
4.21.8 PDFR Demonstration
144(1)
4.21.9 XIU-Accumulator Evaluation
144(2)
4.21.10 Input Mismatch Observation
146(3)
4.21.11 The Flying-Adder Fractional Divider Used Inside PLL
149(2)
4.21.12 The Integer-Flying-Adder PLL
151(3)
4.22 Time-Average-Frequency and Setup Constraint: Revisit
154(2)
4.23 Sense the Frequency Difference: The Time-Average-Frequency Way
156(1)
4.24 Flying-Adder and Direct Digital Synthesis (DDS): The Difference
157(1)
4.25 Flying-Adder for Phase (Delay) Synthesis
158(4)
4.26 Flying-Adder for Duty Cycle Control
162(1)
4.27 Flying-Adder Synthesizer in Reducing the Number of PLLs in SoC
163(4)
Bibliography
164(3)
5 Digital-To-Frequency Converter
167(44)
5.1 Two Ways of Representing Information
167(1)
5.2 The Converters for Transforming Information
168(2)
5.3 The Two Cornerstones of the Digital-to-Frequency Converter
170(2)
5.4 The Theoretical Foundation of Flying-Adder Digital-to-Frequency Converter
172(21)
5.4.1 Flying-Adder DFC Mathematical Model and Its State Variables
173(1)
5.4.2 Flying-Adder DFC as a Finite State Machine (FSM)
174(1)
5.4.3 The Periodicity in Discrete Time Domain
175(1)
5.4.4 The Periodicity in Continuous Time Domain
176(8)
5.4.5 The Time-Average-Frequency
184(1)
5.4.6 Pulse and Cycle in Time-Average-Frequency Signal
185(1)
5.4.7 Timing Irregularity in the Time-Average-Frequency Signal
186(2)
5.4.8 The Sample and Hold Method for Modeling DFC Output
188(2)
5.4.9 Frequency Spectrum of DFC Output
190(1)
5.4.10 Amplitude of the Time-Average-Frequency
191(2)
5.4.11 Relates the Mathematic Model with Real Circuit
193(1)
5.5 Convert the Spurious Energy to Noise Energy
193(5)
5.6 Move Spurs Around
198(3)
5.7 Spread the Energy
201(4)
5.8 Performance Merits
205(6)
Bibliography
208(3)
6 The New Frontier In Electronic System Design
211(68)
6.1 The Clocking Challenges in Reality
211(5)
6.1.1 The Environment
211(1)
6.1.2 Clock Signal for Computation
212(1)
6.1.3 Clock Signal for Synchronization
213(2)
6.1.4 IP Reference, Driving ADC/DAC, Frequency Conversion
215(1)
6.1.5 Frequency Multiplier versus Frequency Generator
216(1)
6.2 Flying-Adder and Its Three Major Application Areas
216(2)
6.3 Flying-Adder for On-chip Frequency Generation
218(4)
6.4 Flying-Adder as Adaptive Clock Generator
222(8)
6.5 Flying-Adder as On-chip VCXO
230(7)
6.6 Flying-Adder for Frame Rate Synchronization and Display Monitor Accommodation
237(3)
6.7 Flying-Adder for Frequency Synchronization in Digital Communication: A Preview
240(2)
6.8 Flying-Adder for Clock Data Recovery
242(13)
6.9 Flying-Adder DLL for Deskew
255(1)
6.10 Flying-Adder for Digital Frequency-Locked Loop (Flying-Adder DFLL)
256(6)
6.11 Flying-Adder for Digital Phase-Locked Loop (Flying-Adder DPLL)
262(1)
6.12 Flying-Adder Technology for Dynamic Frequency Scaling
262(2)
6.13 Flying-Adder as 1-bit DDFS
264(1)
6.14 Flying-Adder for Spread Spectrum Clocking
265(3)
6.15 Flying-Adder for Driving Sampling System
268(3)
6.16 Flying-Adder for Non-uniform Sampling
271(2)
6.17 Flying-Adder as Digital FSK Modulator
273(1)
6.18 Flying-Adder for PWM/PFW DC-DC Power Conversion
274(1)
6.19 Integrate Clocking Chips into Processing Chips
275(4)
Bibliography
276(3)
7 Looking Into Future: The Era Of "Time"
279(8)
7.1 The Four Fundamental Technologies in Modern Chip Design
279(2)
7.2 "Time"-Based Analog Processing
281(2)
7.3 "Time" and Frequency: Encoding Messages Through Modulation
283(1)
7.4 Manipulate "Time": The Tools
283(1)
7.5 It Is Time to Use "Time"
284(3)
7.5.1 But, Does This Make Sense?
284(1)
7.5.2 And, Is It Worth It?
285(1)
7.5.3 Will It Replace Level?
285(1)
7.5.4 Finally, Is It Ready?
285(2)
APPENDICES
287(34)
Appendix 4.A The VHDL Code for Flying-Adder Synthesizer
287(9)
Appendix 4.B How Close Can It Reach an Integer?
296(3)
Appendix 4.C The Seed and Set in Integer-Flying-Adder PLL
299(3)
Appendix 4.D The Number of Carries From an XIU-Accumulator
302(1)
Appendix 5.A The Flying-Adder State Machine Model (perl)
303(4)
Appendix 5.B The Flying-Adder Waveform Generator (perl)
307(3)
Appendix 5.C The Flying-Adder Waveform Generator with Triangular Modulation (perl)
310(4)
Appendix 5.D The Flying-Adder Waveform Generator with Random Modulation (perl)
314(4)
Appendix 6.A The FA-DCXO Tangent Line and Linearity Measurement
318(3)
Index 321
LIMING XIU is Chief Clock Architect at the Novatek Microelectronics Corporation and formerly a senior member of the technical staff at Texas Instruments Inc. Xiu served as vice president of the IEEE Circuits and System Society during 2009–2010. He has written numerous journal and conference papers, holds a number of patents, and is the author of VLSI Circuit Design Methodology Demystified from Wiley-IEEE Press.
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97811183479426e.html
Märksõnad: