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E-raamat: Nanometer Variation-Tolerant SRAM: Circuits and Statistical Design for Yield

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  • Formaat: PDF+DRM
  • Ilmumisaeg: 26-Sep-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461417491
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Nanometer Variation-Tolerant SRAM: Circuits and Statistical Design for YieldSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 26-Sep-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461417491
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"Variability is one of the most challenging obstacles for IC design in nanometer regime. In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost, while achieving higher performance and density. Nanometer Variation-Tolerant SRAM: Circuits and Statistical Design for Yield is the main resource of robust SRAM circuits and statistical design methodologies for researchers and practicing engineers in the field of memory design. This book combines state of the art circuit techniques and statistical methodologies to optimize SRAM performance and yield in nanometer technologies. It is an essential reference for researches, professionals and students working on SRAM design and digital circuits in general"--

This essential reference combines state-of-the-art circuit techniques and statistical methodologies to optimize SRAM performance and yield in nanometer technologies. It shows designers how to apply practical techniques that optimize memory yield.

Variability is one of the most challenging obstacles for IC design in the nanometer regime. In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost, while achieving higher performance and density. With the drastic increase in memory densities, lower supply voltages, and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power.This book is an invaluable reference on robust SRAM circuits and statistical design methodologies for researchers and practicing engineers in the field of memory design. It combines state of the art circuit techniques and statistical methodologies to optimize SRAM performance and yield in nanometer technologies. Provides comprehensive review of state-of-the-art, variation-tolerant SRAM circuit techniques; Discusses Impact of device related process variations and how they affect circuit and system performance, from a design point of view;Helps designers optimize memory yield, with practical statistical design methodologies and yield estimation techniques.
1 Introduction
1(4)
1.1 Motivation: Variation-Tolerant SRAM Design
1(1)
1.2 Book Outline
2(3)
References
3(2)
2 Variability in Nanometer Technologies and Impact on SRAM
5(44)
2.1 SRAM Scaling Trends
5(1)
2.2 Classification of Sources of Variation
6(2)
2.3 Device Variability
8(10)
2.3.1 Random Dopant Fluctuations
8(2)
2.3.2 Line Edge Roughness
10(2)
2.3.3 Random Telegraph Noise
12(3)
2.3.4 Time-Dependent Degradation and Aging
15(1)
2.3.5 Other Sources
16(1)
2.3.6 Highly Scaled Devices: FinFET
17(1)
2.4 Interconnect Variability
18(2)
2.5 Environmental Variability
20(1)
2.6 SRAM Failure Mechanisms
21(12)
2.6.1 Bitcell Stability Failures
21(5)
2.6.2 Impact of Variations on SRAM Vmin
26(4)
2.6.3 Radiation-Induced Soft Errors
30(2)
2.6.4 Hard (Catastrophic) Fails
32(1)
2.7 Techniques to Deal with Variability for Logic Circuits
33(7)
2.7.1 Circuits
34(4)
2.7.2 Architecture
38(2)
2.7.3 Statistical Timing Analysis
40(1)
2.8 Summary
40(9)
References
41(8)
3 Variation-Tolerant SRAM Write and Read Assist Techniques
49(48)
3.1 Introduction
49(1)
3.2 SRAM Stability Metrics
49(9)
3.2.1 Static Write Margin
50(1)
3.2.2 Dynamic Write Margin
51(3)
3.2.3 Static Read Stability
54(2)
3.2.4 Dynamic Read Stability
56(2)
3.3 Bitcell Design for Low Voltage Operation
58(3)
3.4 Write and Read Assist Circuits
61(1)
3.5 Dual Supply Assist Techniques
62(5)
3.6 Single Supply Write and Read Assist Techniques
67(9)
3.6.1 Supply Collapse Write Assist
68(2)
3.6.2 Negative Bitline Write Assist
70(2)
3.6.3 Wordline Boosting Write Assist
72(2)
3.6.4 Wordline Under-Drive Read Assist
74(1)
3.6.5 Lower Bitline Read Assist
75(1)
3.6.6 Short Bitline Read Assist
75(1)
3.6.7 Read and Write Back Assist
75(1)
3.7 Case Study: Selective Precharge Read Assist Technique
76(7)
3.7.1 Circuit Operation
78(2)
3.7.2 Access Time Improvement
80(3)
3.8 Results and Discussion
83(8)
3.9 Summary
91(6)
References
91(6)
4 Reducing SRAM Power Using Fine-Grained Wordline Pulse Width Control
97(22)
4.1 Introduction
97(1)
4.2 Motivation
98(1)
4.3 Yield and Power Tradeoff
99(4)
4.4 Derivation of the Probability Density Function of Twl (PTwl)
103(2)
4.5 Fine-Grained Wordline Pulse Width Control
105(3)
4.5.1 SRAM Built-in Self-Test
106(1)
4.5.2 WL Programable Delay Elements
107(1)
4.5.3 Pulse Width Control Logic
107(1)
4.5.4 System Operation
107(1)
4.6 Results and Discussion
108(6)
4.7 Summary
114(5)
References
115(4)
5 A Methodology for Statistical Estimation of Read Access Yield in SRAMs
119(36)
5.1 Challenges of SRAM Statistical Design
119(1)
5.2 Estimating SRAM Failure Probability
120(10)
5.2.1 Direct Monte Carlo
120(1)
5.2.2 Errors Associated with Monte Carlo
121(1)
5.2.3 Compact Modeling
122(1)
5.2.4 Sensitivity Analysis
122(2)
5.2.5 Importance Sampling
124(2)
5.2.6 Most Probable Failure Point
126(2)
5.2.7 Statistical Blockade
128(2)
5.3 Read Access Yield and SRAM Performance Tradeoff
130(3)
5.4 Modeling of Read Access Failures
133(8)
5.4.1 Read Current and Sensing Slope Variations
134(1)
5.4.2 Sense Amplifier Variations
134(3)
5.4.3 Sensing Window Variations
137(2)
5.4.4 Pass-Gate Leakage
139(2)
5.5 Proposed Yield Estimation Flow
141(2)
5.6 Experimental Results
143(7)
5.7 Summary
150(5)
References
150(5)
6 Characterization of SRAM Sense Amplifier Input Offset for Yield Prediction
155(14)
6.1 Introduction
155(1)
6.2 SRAM Read Access Yield Sensitivity to SA Offset
156(2)
6.3 Sense Amplifier Offset Monitor Implementation
158(2)
6.4 Results and Discussion
160(5)
6.5 Summary
165(4)
References
165(4)
Index 169
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