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E-raamat: Network Infrastructure and Architecture: Designing High-Availability Networks

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(University of Alberta in Edmonton), (Stevens Institute of Technology, AT&T, Red Bank, New Jersey), (PMC-Sierra, Inc.)
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  • Ilmumisaeg: 31-Mar-2008
  • Kirjastus: Wiley-Interscience
  • Keel: eng
  • ISBN-13: 9780470253519
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Network Infrastructure and Architecture: Designing High-Availability NetworksSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 31-Mar-2008
  • Kirjastus: Wiley-Interscience
  • Keel: eng
  • ISBN-13: 9780470253519
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This introduction to high-speed networking technologies and protocols offers advanced students and professionals a view of high-speed networking from the physical layer perspective, covering the ideas underlying networks, the architecture of network elements, and the implementation of these elements in optical and VLSI technologies. Additionally, it focuses on areas not widely covered in existing books, such as physical transport and switching, the process and technique of building networking hardware, and new technologies being deployed in the marketplace. Material is presented in five sections on optical transmission, networking protocols, VLSI chips, data switching, and networking elements and design. Case studies, examples, and exercises are included, along with chapter goals, summaries, and key points. Iniewski is a technology consultant. Annotation ©2008 Book News, Inc., Portland, OR (booknews.com)

This book takes a unique approach to the subject by covering the ideas underlying networks, the architecture of the network elements, and the implementation of these elements in optical and VLSI technologies. Additionally, it focuses on areas not widely covered in existing books: physical transport and switching, the process and technique of building networking hardware, and new technologies being deployed in the marketplace, such as Metro Wave Division Multiplexing (MWDM), Resilient Packet Rings (RPR), Optical Ethernet, and more.
Preface xvii
PART I OPTICAL TRANSMISSION
Introduction to Networking
1(30)
Introduction
1(1)
Transmission Media
2(4)
Copper Wire
2(1)
Coaxial Cable
3(1)
Optical Fiber
4(1)
Wireless Communication
5(1)
Basic Networking Concepts
6(10)
LAN, SAN, MAN, and WAN
6(3)
Network Topologies
9(2)
Circuit vs. Packet Switching
11(2)
Wavelength vs. Time vs. Statistical Multiplexing
13(3)
Open System Interconnection Model
16(4)
Basic Concept
16(1)
OSI Model and Data Encapsulation
17(2)
Network Overlay Hierarchy
19(1)
Networking Equipment
20(11)
Regenerators, Modems, Hubs, and Add--Drop Multiplexers
21(1)
Switches
22(1)
Routers
22(2)
Networking Service Models
24(2)
Key Points
26(2)
References
28(3)
Filer-Optic Transmission
31(56)
Introduction
31(1)
Fiber Optic Communication
32(7)
Why Optical Fiber?
32(3)
Propagation: Single- and Multimode Fibers
35(4)
Light Emission and Detection
39(7)
Light Sources
39(5)
Photodetectors
44(2)
Optical Modulation
46(9)
Direct Modulation
46(1)
External Modulation
47(8)
Optical Amplification
55(7)
Erbium-Doped Fiber Amplifiers
56(3)
Raman Amplifiers
59(2)
EDFA vs. Raman Amplifier
61(1)
Fiber Transmission Impairments
62(25)
Chromatic Dispersion
63(3)
Dispersion Management Techniques
66(6)
Polarization Mode Dispersion
72(5)
Nonlinear Effects
77(5)
Key Points
82(1)
Acknowledgments
83(1)
References
84(3)
Wavelength-Division Multiplexing
87(24)
Introduction
87(1)
WDM Technology
88(7)
WDM Basics
88(1)
WDM Bandwidth Capacity
89(2)
Coarse vs. Dense WDM Systems
91(1)
Future Extensions of DWDM Capacity
92(3)
Networking Equipment for WDM
95(7)
WDM Regenerators
95(1)
Optical Cross-Connects and Switches
96(4)
Optical Add--Drop Multiplexers
100(2)
WDM Networks
102(3)
WDM Network Provisioning
102(1)
Wavelength Blocking
103(1)
O-E-O Conversion in WDM Networks
104(1)
WDM Network Protection
105(1)
Case Study: WDM Link Design
105(6)
Key Points
108(1)
References
109(2)
PART II NETWORKING PROTOCOLS
Sonet
111(26)
Introduction
111(1)
SONET Networks
112(5)
SONET Transmission Rates
112(1)
SONET Network Architectures
113(4)
SONET Framing
117(11)
STS-1 Building Block
117(3)
Synchronous Payload Envelope
120(5)
SONET Virtual Tributaries
125(2)
SDH vs. SONET
127(1)
SONET Equipment
128(1)
SONET O-E-O Regenerator
128(1)
SONET ADM Multiplexer
128(1)
SONET Terminal Multiplexer
129(1)
SONET Implementation Features
129(8)
SONET Scrambling
129(1)
SONET Clock Distribution
130(3)
SONET Byte Stuffing
133(1)
Key Points
134(1)
References
135(2)
TCP/IP Protocol Suite
137(46)
Introduction
138(1)
Structure of the Protocol Suite
138(7)
Internet Protocol
145(3)
IP Addresses
145(1)
IP Header Format and Function
146(2)
User Datagram Protocol
148(1)
Transmission Control Protocol
149(6)
TCP Header Format and Function
151(2)
Connection-Oriented Service
153(1)
Receiver Window
153(2)
TCP Flow Control
155(12)
Receiver-Based Flow Control
156(6)
Transmitter-Based Flow Control
162(3)
Fast Retransmit and Fast Recovery
165(1)
Delayed Acknowledgment
166(1)
Naigle's Algorithm
167(1)
IP Routing Mechanisms
167(2)
IP Route Calculations
169(5)
Difficulties with TCP and IP
174(4)
One Shortest Route, Regardless of Load Conditions
174(1)
Deliberate Congestion and Backoff
175(1)
Lack of Quality-of-Service Support
175(1)
Receiver Windows and Round-Trip Times
175(2)
Long, Fat TCP Pipes
177(1)
Big Packets on Thin Pipes
178(1)
IPv6: The Future?
178(2)
Conclusions
180(3)
Key Points
180(1)
References
181(2)
Protocol Stacks
183(36)
Introduction
183(2)
Difficulties with the TCP/IP Protocol Suite
185(2)
Supporting Protocols
187(17)
ATM
188(2)
Generic Framing Procedure
190(2)
Multiprotocol Label Switching
192(3)
Ethernet over the Internet
195(1)
Resilient Packet Rings
196(4)
G.709: Digital Wrapper Technology
200(4)
Legacy Solutions
204(1)
IP over SONET
204(1)
IP over ATM over SONET
204(1)
New Protocol Stack Solutions
205(14)
Using MPLS
205(2)
Future All- or Mostly Optical Networks
207(3)
Gigabit Ethernet over the Internet
210(1)
Storage Area Network Protocols over the Internet
211(4)
Key Points
215(2)
References
217(2)
PART III VLSI CHIPS
VLSI Integrated Circuits
219(46)
Introduction
220(3)
Integrated Circuits, VLSI, and CMOS
220(1)
Classification of Integrated Circuits
221(2)
Looking Ahead
223(1)
Integrated Circuits for Data Networking
223(8)
PMD and PHY Devices (Layer 1)
225(2)
Framers and Mappers (Layer 2)
227(3)
Packet Processing Devices (Layer 3)
230(1)
Chip I/O Interfaces
231(16)
Serial vs. Parallel I/O
232(2)
Networking I/O Standards
234(6)
Design of Data Networking I/O Interfaces
240(3)
Memory I/O Interfaces
243(2)
Microprocessor I/O Interfaces
245(2)
Examples of Chip Architectures
247(6)
Time-Slice Architecture
247(3)
SONET Framer Architecture
250(2)
Network Processor Architecture
252(1)
VLSI Design Methodology
253(12)
Design Specification
257(1)
Functional Design and RTL Coding
257(2)
Functional Verification
259(1)
Design Synthesis
260(1)
Physical Design and Verification
260(1)
Key Points
261(2)
Acknowledgments
263(1)
References
263(2)
Circuits for Optical-to-Electrical Conversion
265(28)
Introduction
265(1)
Optical to Electrical-to-Optical Conversion
266(6)
Principle of Operation
266(1)
Optical Transceiver Architectures
267(1)
Integrated Circuit Technology for Optical Transceivers
268(4)
Signal Amplification
272(3)
Trans-Impedance Amplifier
272(1)
Limited Amplifier
273(1)
Laser Driver
274(1)
Phase-Locked Loop
275(4)
Phase-Locked-Loop Architecture
275(1)
Voltage-Controlled Oscillator
275(3)
Phase and Frequency Detectors
278(1)
Clock Synthesis and Recovery
279(8)
Clock Synthesis
279(4)
Clock and Data Recovery
283(2)
Jitter Requirements
285(2)
Preemphasis and Equalization
287(6)
High-Speed Signal Impairments
287(2)
Preemphasis
289(1)
Equalization
289(1)
Key Points
290(1)
References
290(3)
PART IV DATA SWITCHING
Physical Circuit Switching
293(50)
Introduction
293(1)
Switching and Why It Is Important
294(4)
Three Types of Switching
298(2)
Switching of Physical Circuits
298(1)
Switching of Time-Division-Multiplexed Signals
299(1)
Switching of Cell and/or Packets
300(1)
Quality of Service
300(2)
Special Services
302(1)
Switching in One or More Stages
303(1)
Cost Model for Switch Implementations
304(1)
Crossbar Switch Concept
305(3)
Optical Crossbar Switches
308(2)
Digital Electronic Crossbar Switches
310(8)
Control of Digital Crossbar Switches
314(1)
Cost Model for Digital Electronic Crossbar Switches
315(2)
Growth Limits of Digital Electronic Crossbar Switches
317(1)
Commercial Examples of Electronic Crossbar Switches
317(1)
Multistage Crossbar-Based Switches
318(21)
Routing and Blocking in Clos Networks
321(11)
Multicast in Clos Networks
332(6)
Implementation Costs of Clos Networks
338(1)
Desirability of Single-Stage Fabrics and Limits to Multistage Fabrics
339(4)
Key Points
340(1)
References
341(2)
Time-Division-Multipleured Switching
343(40)
Introduction
343(1)
TDM Review
344(2)
TDM Switching Problem
346(4)
Temporal Alignment
348(1)
Dual Control Pages
349(1)
Strictly Nonblocking Design
349(1)
Varying Port Configurations
350(1)
Central Memory TDM Switches
350(5)
Cost Model for Central Memory TDM Switches
352(1)
Limits of Central Memory Design
353(2)
Ingress Buffered TDM Switches
355(2)
Egress Buffered Self-Select TDM Switches
357(1)
Sliced Single-Stage SNB TDM Fabrics
358(4)
Time--Space Multistage TDM Fabrics
362(15)
Architecture and Costs of Time--Space--Time Switch Fabrics
365(1)
Blocking and OPA
366(8)
Space--Time--Space Switching
374(3)
Multistage Memory Switches
377(2)
Summary
379(4)
Key Points
380(1)
References
381(2)
Packet and Cell Switching and Queuing
383(48)
Introduction
384(1)
Packet--Cell Switching Problem
384(2)
Traffic Patterns
386(3)
Realistic Loads
387(1)
Responses to Congestion
388(1)
Logical Queue Structures and Their Behavior
389(11)
Queues
389(1)
Flows and Logical Queues
390(1)
Queuing Systems
390(2)
Speedup and Blocking
392(3)
Possible Queuing Systems
395(5)
Queue Locations and Buffer Sharing
400(4)
Filling and Draining Queues
404(2)
Filling
404(1)
Draining
405(1)
Central Memory Packet--Cell Switches
406(4)
Ingress Buffered Packet--Cell Switches
410(3)
Blocking Ingress-Buffered Frame Switches
410(2)
Nonblocking Ingress-Buffered Frame Switches
412(1)
Request--Grant Cell Switches
413(12)
Use of Cells
414(1)
Request--Grant Protocol
415(1)
Permutation Arbitration by Wavefront Computation
416(9)
Sliced Request--Grant Switches
425(1)
Multistage Frame Networks
425(1)
Multicast
426(5)
Multicast in the Blocking Ingress-Buffered Architecture
428(1)
Multicast in the Nonblocking Ingress-Buffered Architecture
428(1)
Multicast in the Request--Grant Architecture
428(1)
Key Points
429(2)
PART V NETWORKING
Network Elements
431(48)
Introduction
431(1)
Networking Functions
432(28)
Information Transfer and Regeneration Function
438(2)
Multiplexing Function
440(5)
Grooming Function
445(3)
Switching Function
448(4)
Routing Function
452(8)
Networking Equipment
460(13)
Regeneration Equipment
460(2)
Grooming Equipment
462(1)
Multiplexing Equipment
462(2)
Switching Equipment
464(8)
Routing Equipment
472(1)
Summary
473(6)
Key Points
473(3)
References
476(3)
Network Design: Efficient, Survivable Networks
479(54)
Introduction
479(2)
Sonet
481(7)
Overview
481(2)
Protection Switching
483(5)
Optical Transport Network
488
Motivations, Goals, and Approaches
488(6)
OTN Standards Support
494(4)
Basic OTN Technical Concepts
498(2)
OTN Deployments
500
Automatically Switched Optical Networks
50(477)
Overview
501(2)
Standardization Efforts
503(14)
Architectural Principles for ASON
517(10)
Status and Deployments
527(6)
Key Points
528(3)
References
531(2)
Index 533
Krzysztof Iniewski, PhD, is a founder and President of CMOS Emerging Technologies, Inc., a high-technology consulting company in Vancouver, Canada. Previously, Dr. Iniewski served as a university professor and R&D manager. He holds twenty-eight international patents and is a Senior Member of the IEEE. He is an editor of Wireless Technologies: Circuits, Systems, and Devices; VLSI Circuits: A System Perspective; and VLSI Circuits for Bio-Medical Applications.

Carl McCrosky, PhD, is a Professor of Electrical and Computer Engineering at the University of Saskatchewan (Canada). Previously, Dr. McCrosky was principal engineer with PMC-Sierra, Inc., professor of computer science at the University of Saskatchewan, chief scientist of HyperCore, Inc., and a partner in Andyne Computing, Ltd.

Daniel Minoli has worked and published extensively in the technology field, with more than thirty years of hands-on experience in networking, IT, telecommunications, wireless, and video/IPTV. He has helped develop systems and solutions for such organizations as SES Americom, Prudential Securities, AT&T, Telcordia, New York University, Stevens Institute of Technology, and more.
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