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E-raamat: Networks-on-Chips: Theory and Practice

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The 11 contributions in this collection examine 3D network on a chip (NoC) architectures, resource allocation, processor traffic modeling, formal verification, protocols at different levels of abstraction, quality of service, testing and verification, security requirements, real-time monitoring, and power constraints. The CHAIN works, an industrial design flow from Silistix, is introduced to address the complex issues of combining various design techniques using NoC technology. A case study of Multiprocessor SoC for video encoding applications is presented using Arteris NoC. The editors are affiliated with the Electrical and Computer Engineering Department at the University of Victoria in Canada. Annotation ©2009 Book News, Inc., Portland, OR (booknews.com)

The implementation of networks-on-chip (NoC) technology in VLSI integration presents a variety of unique challenges. To deal with specific design solutions and research hurdles related to intra-chip data exchange, engineers are challenged to invoke a wide range of disciplines and specializations while maintaining a focused approach.

Leading Researchers Present Cutting-Edge Designs Tools
Networks-on-Chips: Theory and Practice facilitates this process, detailing the NoC paradigm and its benefits in separating IP design and functionality from chip communication requirements and interfacing. It starts with an analysis of 3-D NoC architectures and progresses to a discussion of NoC resource allocation, processor traffic modeling, and formal verification, with an examination of protocols at different layers of abstraction.

An exploration of design methodologies, CAD tool development, and system testing, as well as communication protocol, the text highlights important emerging research issues, such as

  • Resource Allocation for Quality of Service (QoS) on-chip communication

  • Testing, verification, and network design methodologies

  • Architectures for interconnection, real-time monitoring, and security requirements

  • Networks-on-Chip Protocols

Presents a flexible MPSoC platform to easily implement multimedia applications and evaluate future video encoding standards

This useful guide tackles power and energy issues in NoC-based designs, addressing the power constraints that currently limit the embedding of more processing elements on a single chip. It covers traffic modeling and discusses the details of traffic generators.

Using unique case studies and examples, it covers theoretical and practical issues, guiding readers through every phase of system design.

Preface vii
About the Editors xi
Contributors xiii
1 Three-Dimensional Networks-on-Chip Architectures 1
Alexandros Bartzas, Kostas Siozios, and Dimitrios Soudris
1.1 Introduction
1
1.2 Related Work
3
1.3 Alternative Vertical Interconnection Topologies
5
1.4 Overview of the Exploration Methodology
7
1.5 Evaluation—Experimental Results
9
1.5.1 Experimental Setup
9
1.5.2 Routing Procedure
12
1.5.3 Impact of Traffic Load
13
1.5.4 3D NoC Performance under Uniform Traffic
14
1.5.5 3D NoC Performance under Hotspot Traffic
16
1.5.6 3D NoC Performance under Transpose Traffic
19
1.5.7 Energy Dissipation Breakdown
19
1.5.8 Summary
22
1.6 Conclusions
23
Acknowledgments
23
References
24
2 Resource Allocation for QoS On-Chip Communication 29
Axel Jantsch and Zhonghai Lu
2.1 Introduction
29
2.2 Circuit Switching
33
2.3 Time Division Multiplexing Virtual Circuits
37
2.3.1 Operation and Properties of TDM VCs
38
2.3.2 On-Chip TDM VCs
39
2.3.3 TDM VC Configuration
40
2.3.4 Theory of Logical Network for TDM VCs
41
2.3.5 Application of the Logical Network Theory for TDM VCs
44
2.4 Aggregate Resource Allocation
46
2.4.1 Aggregate Allocation of a Channel
46
2.4.2 Aggregate Allocation of a Network
51
2.5 Dynamic Connection Setup
53
2.6 Priority and Fairness
56
2.7 QoS in a Telecom Application
58
2.7.1 Industrial Application
58
2.7.2 VC Specification
59
2.7.3 Looped VC Implementation
60
2.8 Summary
62
References
62
3 Networks-on-Chip Protocols 65
Michihiro Koibuchi and Hiroki Matsutani
3.1 Introduction
66
3.2 Switch-to-Switch Flow Control
67
3.2.1 Switching Techniques
67
3.2.1.1 Store-and-Forward (SAF) Switching
67
3.2.1.2 Wormhole (WH) Switching
67
3.2.1.3 Virtual Cut-Through (VCT) Switching
68
3.2.2 Channel Buffer Management
70
3.2.2.1 Go & Stop Control
70
3.2.2.2 Credit-Based Control
70
3.2.3 Evaluation
71
3.2.3.1 Throughput and Latency
71
3.2.3.2 Amount of Hardware
71
3.3 Packet Routing Protocols
73
3.3.1 Deadlocks and Livelocks of Packet Transfer
73
3.3.2 Performance Factors of Routing Protocols
74
3.3.3 Routing Algorithm
77
3.3.3.1 k-ary n-cube Topologies
78
3.3.3.2 Irregular Topologies
80
3.3.4 Subfunction of Routing Algorithms
82
3.3.4.1 Output Selection Function (OSF)
83
3.3.4.2 Path Selection Algorithm
83
3.3.5 Evaluation
83
3.4 End-to-End Flow Control
84
3.4.1 Injection Limitation
85
3.4.2 ACK/NACK Flow Control
85
3.5 Practical Issues
86
3.5.1 Commercial and Prototype NoC Systems
86
3.5.2 Research Trend
88
3.6 Summary
90
References
91
4 On-Chip Processor Traffic Modeling for Networks-on-Chip Design 95
Antoine Scherrer, Antoine Fraboulet, and Tanguy Risset
4.1 Introduction
96
4.2 Statistical Traffic Modeling
97
4.2.1 On-Chip Processor Traffic
97
4.2.2 On-Chip Traffic Formalism
98
4.2.3 Statistical Traffic Modeling
99
4.2.4 Statistical Stationarity and Traffic Phases
100
4.2.4.1 Phase Decomposition
101
4.2.5 Long-Range Dependence
102
4.2.5.1 Estimation of the Hurst Parameter
103
4.2.5.2 Synthesis of Long-Range Dependent Processes
103
4.3 Traffic Modeling in Practice
104
4.3.1 Guidelines for Designing a Traffic Modeling Environment
105
4.3.1.1 Simulation Precision
105
4.3.1.2 Trace Analysis
105
4.3.1.3 Platform Generation
106
4.3.1.4 Traffic Analysis and Synthesis Flow
106
4.3.2 Multiphase Traffic Generation Environment
106
4.3.2.1 Key Features of the MPTG Environment
112
4.3.3 Experimental Analysis of NoC Traffic
112
4.3.3.1 Speedup
112
4.3.3.2 Simulation Setup
113
4.3.3.3 Multiphase
114
4.3.3.4 Long-Range Dependence
115
4.3.4 Traffic Modeling Accuracy
117
4.4 Related Work and Conclusion
118
References
119
5 Security in Networks-on-Chips 123
Leandro Fiorin, Gianluca Palermo, Cristina Silvano, and Mariagiovanna Sami
5.1 Introduction
124
5.2 Attack Taxonomy
125
5.2.1 Attacks Addressing SoCs
125
5.2.1.1 Software Attacks
126
5.2.1.2 Physical Attacks
126
5.2.2 Attacks Exploiting NoC Implementations
130
5.2.2.1 Denial of Service
131
5.2.2.2 Illegal Access to Sensitive Information
133
5.2.2.3 Illegal Configuration of System Resources
133
5.2.3 Overview of Security Enhanced Embedded Architectures
133
5.3 Data Protection for NoC-Based Systems
135
5.3.1 The Data Protection Unit
135
5.3.2 DPU Microarchitectural Issues
137
5.3.3 DPU Overhead Evaluation
139
5.4 Security in NoC-Based Reconfigurable Architectures
140
5.4.1 System Components
140
5.4.1.1 Security and Configuration Manager
140
5.4.1.2 Secure Network Interface
140
5.4.1.3 Secure Configuration of NIs
142
5.4.2 Evaluation of Cost
142
5.5 Protection from Side-Channel Attacks
143
5.5.1 A Framework for Cryptographic Keys Exchange in NoCs
143
5.5.1.1 Secure Messages Exchange
145
5.5.1.2 Download of New Keys
146
5.5.1.3 Other Applications
148
5.5.1.4 Implementation Issues
148
5.5.2 Protection of IP Cores from Side Channel Attacks
148
5.5.2.1 Countermeasures to Side-Channel Attacks
149
5.6 Conclusions
150
5.7 Acknowledgments
151
References
151
6 Formal Verification of Communications in Networks-on-Chips 155
Dominique Borrione, Amr Helmy, Laurence Pierre, and Julien Schmaltz
6.1 Introduction: Validation of NoCs
156
6.1.1 Main Issues in NoC Validation
156
6.1.2 The Generic Network-on-Chip Model
157
6.1.3 State-of-the-Art
158
6.2 Application of Formal Methods to NoC Verification
160
6.2.1 Smooth Introduction to Formal Methods
160
6.2.2 Theorem Proving Features
161
6.3 Meta-Model and Verification Methodology
164
6.4 A More Detailed View of the Model
165
6.4.1 General Assumptions
165
6.4.1.1 Computations and Communications
165
6.4.1.2 Generic Node and State Models
165
6.4.2 Unfolding GeNoC: Data Types and Overview
167
6.4.2.1 Interfaces
167
6.4.2.2 Network Access Control
168
6.4.2.3 Routing
168
6.4.2.4 Scheduling
168
6.4.2.5 GeNoC and GenocCore
169
6.4.2.6 Termination
169
6.4.2.7 Final Results and Correctness
169
6.4.3 GeNoC and GenocCore: Formal Definition
170
6.4.4 Routing Algorithm
171
6.4.4.1 Principle and Correctness Criteria
171
6.4.4.2 Definition and Validation of Function Routing
173
6.4.5 Scheduling Policy
173
6.5 Applications
174
6.5.1 Spidergon Network and Its Packet-Switched Mode
174
6.5.1.1 Spidergon: Architecture Overview
174
6.5.1.2 Formal Model Preliminaries: Nodes and State Definition
176
6.5.1.3 Instantiating Function Routing: SpidergonRouting
176
6.5.1.4 Instantiating Function Scheduling: PacketScheduling
178
6.5.1.5 Instantiation of the Global Function GeNocCore
180
6.5.2 The Hermes Network and its Wormhole Switching Technique
180
6.5.2.1 Hermes: Architecture Overview
180
6.5.2.2 Formal Model Preliminaries: Nodes and State Definition
181
6.5.2.3 Instantiating Function Routing: XYRouting
181
6.5.2.4 Instantiating Function Scheduling: Wormhole Switching
183
6.5.2.5 Instantiation of the Global Function GeNocCore
185
6.6 Conclusion
185
References
186
7 Test and Fault Tolerance for Networks-on-Chip Infrastructures 191
Partha Pratim Pande, Cristian Grecu, Amlan Ganguly, Andre Ivanov, and Resve Saleh
7.1 Test and Fault Tolerance Issues in NoCs
192
7.2 Test Methods and Fault Models for NoC Fabrics
193
7.2.1 Fault Models for NoC Infrastructure Test
194
7.2.2 Fault Models for NoC Interswitch Links
194
7.2.3 Fault Models for FIFO Buffers in NoC Switches
194
7.2.4 Structural Postrnanufacturing Test
196
7.2.4.1 Test Data Transport
197
7.2.5 Functional Test of NoCs
202
7.2.5.1 Functional Fault Models for NoCs
202
7.3 Addressing Reliability of NoC Fabrics through Error Control Coding
203
7.3.1 Crosstalk Avoidance Coding
204
7.3.2 Forbidden Overlap Condition (FOC) Codes
205
7.3.3 Forbidden Transition Condition (FTC) Codes
206
7.3.4 Forbidden Pattern Condition Codes
207
7.4 Joint Crosstalk Avoidance and Error Control Coding
208
7.4.1 Duplicate Add Parity and Modified Dual Rail Code
209
7.4.2 Boundary Shift Code
210
7.4.3 Joint Crosstalk Avoidance and Double Error Correction Code
211
7.5 Performance Metrics
213
7.5.1 Energy Savings Profile of NoCs in Presence of Coding
213
7.5.2 Timing Constrain is in NoC Interconnection Fabrics in Presence of Coding
218
7.6 Summary
219
References
219
8 Monitoring Services for Networks-on-Chips 223
George Kornaros, Ioannis Papaeystathiou, and Dionysios Pnevmatikatos
8.1 Introduction
224
8.2 Monitoring Objectives and Opportunities
226
8.2.1 Verification and Debugging
226
8.2.2 Network Parameters Adaptation
227
8.2.3 Application Profiling
227
8.2.4 Run-Time Reconfigurability
228
8.3 Monitoring Information in Networks-on-Chips
228
8.3.1 A High-Level Model of NoC Monitoring
228
8.3.1.1 Events
229
8.3.1.2 Programming Model
230
8.3.1.3 Traffic Management
230
8.3.1.4 NoC Monitoring Communication Infrastructure
231
8.3.2 Measurement Methods
231
8.3.3 NoC Metrics
233
8.4 NoC Monitoring Architecture
234
8.5 Implementation Issues
238
8.5.1 Separate Physical Communication Links
239
8.5.2 Shared Physical Communication Links
239
8.5.3 The Impact of Programmability on Implementation
240
8.5.4 Cost Optimizations
241
8.5.5 Monitor-NoC Codesign
242
8.6 A Case Study
244
8.6.1 Software Assisted Monitoring Services
244
8.6.2 Monitoring Services Interacting with OS
245
8.6.3 Monitoring Services at Transaction Level and Monitor-Aware Design Flow
246
8.6.4 Hardware Support for Testing NoC
248
8.6.5 Monitoring for Cost-Effective NoC Design
248
8.6.6 Monitoring for Time-Triggered Architecture Diagnostics
249
8.7 Future Research
250
8.8 Conclusions
251
References
252
9 Energy and Power Issues in Networks-on-Chips 255
Seung Eun Lee and Nader Bagherzadeh
9.1 Energy and Power
257
9.1.1 Power Sources
257
9.1.1.1 Dynamic Power Consumption
258
9.1.1.2 Static Power Consumption
258
9.1.2 Energy Model for NoC
260
9.2 Energy and Power Reduction Technologies in NoC
261
9.2.1 Microarchitecture Level Techniques
261
9.2.1.1 Low-Swing Signaling
261
9.2.1.2 Link Encoding
262
9.2.1.3 RTL Power Optimization
263
9.2.1.4 Multithreshold (Vih) Circuits
263
9.2.1.5 Buffer Allocation
263
9.2.1.6 Performance Enhancement
264
9.2.1.7 Miscellaneous
264
9.2.2 System-Level Techniques
265
9.2.2.1 Dynamic Voltage Scaling
265
9.2.2.2 On-Off Links
268
9.2.2.3 Topology Optimization
269
9.2.2.4 Application Mapping
270
9.2.2.5 Globally Asynchronous Locally Synchronous (GALS)
271
9.3 Power Modeling Methodology for NoC
271
9.3.1 Analytical Model
272
9.3.2 Statistical Model
272
9.4 Summary
274
References
275
10 The CHAIN®works Tool Suite: A Complete Industrial Design Flow for Networks-on-Chips 281
John Bainbridge
10.1 CHAIN® Works
282
10.2
Chapter Contents
283
10.3 CHAIN® NoC Building Blocks and Operation
284
10.3.1 Differences in Operation as Compared to Clocked Interconnect
284
10.3.2 Two-Layer Abstraction Model
285
10.3.3 Link-Level Operation
286
10.3.4 Transmit and Receive Gateways and the CHAIN Gateway Protocol
288
10.3.5 The Protocol Layer Adapters
289
10.4 Architecture Exploration
290
10.4.1 CSL Language
291
10.4.1.1 Global Definitions
292
10.4.1.2 Endpoints and Ports
292
10.4.1.3 Address Maps
294
10.4.1.4 Connectivity Specification
295
10.4.2 NoC Architecture Exploration Using CHAIN®architect
296
10.4.3 Synthesis Algorithm
297
10.4.4 Synthesis Directives
299
10.5 Physical Implementation: Floorplanning, Placement, and Routing
299
10.6 Design-for-Test (DFT)
301
10.7 Validation and Modeling
303
10.7.1 Metastability and Nondeterminism
304
10.7.2 Equivalence Checking
305
10.8 Summary
305
References
306
11 Networks-on-Chip-Based Implementation: MPSoC for Video Coding Applications 307
Dragomir Milojevic, Anthony Leroy, Frederic Robert, Philippe Martin, and Diederik Verkest
11.1 Introduction
308
11.2 Short Survey of Existing Interconnect Solutions
310
11.3 Arteris NoC: Basic Building Blocks and EDA Tools
311
11.3.1 NoC Transaction and Transport Protocol
311
11.3.1.1 Transaction Layer
312
11.3.1.2 Transport Layer
313
11.3.1.3 Physical Layer
313
11.3.2 Network Interface Units
316
11.3.2.1 Initiator NIU Units
317
11.3.2.2 Target NIU Units
318
11.3.3 Packet Transportation Units
319
11.3.3.1 Switching
319
11.3.3.2 Routing
320
11.3.3.3 Arbitration
321
11.3.3.4 Packet Management
321
11.3.4 NoC Implementation Issues
323
11.3.4.1 Pipelining
323
11.3.4.2 Clock Gating
324
11.3.5 EDA Tools for NoC Design Tools
325
11.3.5.1 NoCexplorer
325
11.3.5.2 NoCcompiler
326
11.4 MPSoC Platform
329
11.4.1 ADRES Processor
331
11.4.2 Communication Assist
333
11.4.3 Memory Subsystem
334
11.4.4 NoC
335
11.4.5 Synthesis Results
337
11.5 Power Dissipation of the NoC for Video Coding Applications
340
11.5.1 Video Applications Mapping Scenarios
340
11.5.1.1 MPEG-4 SP Encoder
340
11.5.1.2 AVC/H.264 SP Encoder
341
11.5.2 Power Dissipation Models of Individual NoC Components
345
11.5.2.1 Network Interface Units
345
11.5.2.2 Switches
346
11.5.2.3 Links: Wires
347
11.5.3 Power Dissipation of the Complete NoC
348
References
352
Index 357
Fayez Gebali is a professor in the Department of Electrical and Computer Engineering, University of Victoria, British Columbia, Canada. He is a registered professional engineer and a senior member of the IEEE since 1983. Haytham Elmiligi is a Ph.D. candidate at the same school and was a publication chair for the 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing. M. Watheq El-Kharashi is currently an associate professor in the Department of Computer and Systems Engineering, Ain Shams University, Cairo, Egypt, and is also an adjunct assistant professor in the Department of Electrical and Computer Engineering, University of Victoria.
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