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E-raamat: New Methods of Concurrent Checking

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Computers are everywhere around us. We, for example, as air passengers, car drivers, laptop users with Internet connection, cell phone owners, hospital patients, inhabitants in the vicinity of a nuclear power station, students in a digital library or customers in a supermarket are dependent on their correct operation. Computers are incredibly fast, inexpensive and equipped with almost unimag- able large storage capacity. Up to 100 million transistors per chip are quite common today - a single transistor for each citizen of a large capital city in the world can be 2 easily accommodated on an ordinary chip. The size of such a chip is less than 1 cm . This is a fantastic achievement for an unbelievably low price. However, the very small and rapidly decreasing dimensions of the transistors and their connections over the years are also the reason for growing problems with reliability that will dramatically increase for the nano-technologies in the near future. Can we always trust computers? Are computers always reliable? Are chips suf- ciently tested with respect to all possible permanent faults if we buy them at a low price or have errors due to undetected permanent faults to be discovered by c- current checking? Besides permanent faults, many temporary or transient faults are also to be expected.
1 Introduction 1
2 Physical Faults and Functional Errors 5
2.1 Stuck-At Faults
6
2.2 Bridging Faults
10
2.2.1 Non-Resistive Bridging Faults
10
2.2.2 Resistive Bridging Faults
13
2.3 CMOS Stuck-Open and Stuck-On Faults
17
2.4 Delay Faults
21
2.5 Transient Faults
22
2.6 Functional Error Model
22
2.7 Output Dependencies
24
2.8 Self-Testing and Self-Checking
25
2.9 Faults and Errors in Submicron Technologies
27
3 Principles of Concurrent Checking 31
3.1 Duplication and Comparison
31
3.1.1 Description of the Method
32
3.1.2 Comparators and Two-Rail Checkers
33
3.1.3 Method of Partial Duplication
40
3.2 Block Codes for Error Detection
42
3.2.1 Classical Error Detection Codes
42
3.2.2 Non-linear Split Error Detection Codes
49
3.3 Parity and Group Parity Checking
53
3.3.1 Predictor and Generator Circuits
55
3.3.2 Parity Prediction
57
3.3.3 Generalized Circuit Graph
60
3.3.4 Independent Outputs and Weakly Independent Outputs
62
3.3.5 Determination of Groups of Weakly Independent Outputs
66
3.3.6 Circuit Modification by Node-Splitting
70
3.3.7 Further Methods for the Determination of Weakly Independent Outputs
73
3.4 Odd and Even Error Detection
75
3.4.1 Description of Odd and Even Error Detection
75
3.5 Code-Disjoint Circuits
77
3.5.1 Design of Code-Disjoint Circuits
78
3.6 Error Detection by Complementary Circuits
84
3.6.1 Error Detection by Use of Complementary Circuits
85
3.6.2 Complementary Circuits for 1-out-of-3 Codes
87
3.6.3 Conditions for the Existence of Totally Self-Checking Error Detection Circuits by Complementary Circuits
90
3.7 General Method for the Design of Error Detection Circuits
98
3.7.1 Description of the Method
98
3.8 Self-Dual Error Detection
102
3.8.1 Self-Dual Boolean Functions
103
3.8.2 Transformation of a Given Circuit into a Self-Dual Circuit
104
3.8.3 Self-Dual Error Detection Circuits
107
3.8.4 Self-Dual Fault-Secure Circuits
109
3.9 Error Detection with Soft Error Correction
116
3.9.1 Description of the Method
116
4 Concurrent Checking for the Adders 123
4.1 Basic Types of Adders
124
4.2 Parity Checking for Adders
115
4.3 Self-Checking Adders
138
4.3.1 Self-Checking Carry Look-Ahead Adders
138
4.3.2 Self-Checking Partially Duplicated Carry Skip Adder
151
4.3.3 Self-Checking Carry Select Adders
156
References 173
Index 179