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E-raamat: Noise Coupling in System-on-Chip

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Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community. The flow provides capability to analyze noise components, propagating through the substrate, the parasitic interconnects and the package. Using this book, the reader can analyze and avoid complex noise coupling that degrades RF and mixed signal design performance, while reducing the need for conservative design practices. With chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon. It additionally features case studies that can be found in any modern CMOS SoC product for mobile communications, automotive applications and readout front ends.

Arvustused

"This is one of the most modern books related on the noise coupling in modern Systems on Chip (SoC) design. It addresses the state of the art in the SoC design, covering a wide range of topics, including novel methodologies to identify noise coupling in silicon, interconnect and package helping locate potential noise issues, both before tapeout and even earlier in the design process. The coupling mechanisms are addressed from silicon device level to package and printed circuit board level and from the kHz region until the mm Wave frequency region. Special focus is provided in 3D integration and on Through Silicon Vias coupling mechanisms. In addition, emerging coupling topics are addressed such as thermal and optical interconnects performance, power delivery networks, electro-thermal considerations onto 3D integration and 3D floor planning based on thermal interactions. A strong point of the book is that it has been written by a mixture of industrial experts and academic professors and researchers, providing in-depth theoretical background and discussion of the most important practical aspects. Therefore, this book will be a powerful tool for designers involved with high performance SoC design in both 2D and 3D ICs. Using this book, we able to utilize innovative coupling analysis flow and modeling, addressing all related needs, to analyze noise components, propagating not just through the substrate, but also through the parasitic interconnect and package and to identify substrate coupling noise contributors, levels and transfer functions." Costas Psychalinos, University of Patras, Greece

"This book addresses noise coupling in integrated systems, which is a topic mostly widespread in industrial developmentsThis book could contribute to developing a widespread culture about how to deal with noise coupling in modern integrated systems." Domenico Zito, Aarhus University, Denmark

Preface xi
Acknowledgments xiii
Editor xvii
Contributors xix
Chapter 1 System-on-Chip Substrate Crosstalk Modeling and Simulation Flow 1(20)
Thomas Noulis
Peter Baumgartner
1.1 Introduction
1(3)
1.2 Ring Oscillator Substrate Crosstalk Vehicle
4(2)
1.3 Substrate Crosstalk Modeling and Analysis Flow
6(3)
1.4 Crosstalk Simulation versus Silicon Measurements
9(7)
1.4.1 FFT Processing Optimization
14(2)
1.5 Conclusion and Discussion
16(2)
Acknowledgment
18(1)
References
18(3)
Chapter 2 Substrate Induced Signal Integrity in 2D and 3D ICs 21(24)
Emre Salman
2.1 Introduction
21(1)
2.2 Overview of Substrate Noise Coupling in 2D ICs
22(9)
2.2.1 Substrate Noise Analysis and Modeling
24(7)
2.2.1.1 High-Level Simulation Methods
25(3)
2.2.1.2 Substrate Modeling
28(1)
2.2.2 Substrate Noise Reduction
28(3)
2.3 Figures-of-Merit to Characterize the Significance of Substrate Coupling Noise
31(7)
2.3.1 Concept of Input Referred Switching Noise
31(5)
2.3.2 Reverse Body Biasing to Alleviate Substrate Noise
36(2)
2.4 Implications of 3D Technology on Substrate Noise Coupling
38(2)
2.5 Summary and Conclusions
40(1)
References
40(5)
Chapter 3 TSV-to-Substrate Noise Coupling in 3D Systems 45(18)
Boris Vaisband
Eby G. Friedman
3.1 Introduction
45(1)
3.2 Heterogeneous Substrate and Related Circuit Characteristics
46(1)
3.3 Substrate Noise Models
47(3)
3.3.1 Si Model
47(1)
3.3.2 Ge Model
48(2)
3.3.3 GaAs Model
50(1)
3.4 Model Evaluation
50(4)
3.4.1 COMSOL Evaluation
51(1)
3.4.2 SPICE Evaluation
52(2)
3.5 Noise Mitigation Techniques
54(5)
3.5.1 Guard Rings
55(2)
3.5.2 Distance between Aggressor and Victim
57(1)
3.5.3 Epitaxial Layer
58(1)
3.6 Conclusions
59(1)
References
60(3)
Chapter 4 3D Interconnects with IC's Stack Global Electrical Context Consideration 63(30)
Yue Ma
Olivier Valorge
J.R. Cardenas-Valdez
Francis Calmon
J.C. Nunez-Perez
J. Verdier
Christian Gontrand
4.1 Introduction
63(3)
4.2 Substrate Noise Generators and Propagation
66(12)
4.2.1 ICEM Standard Approach and Its Extension
66(8)
4.2.1.1 Analog Part and Substrate Coupling
67(1)
4.2.1.2 VCO Structure and Layout
68(1)
4.2.1.3 Static Sensitivity Functions
69(3)
4.2.1.4 VCO Spurious Side-Bands Due to Substrate Perturbation
72(2)
4.2.2 Test Chips Presentation
74(2)
4.2.3 Extractions, Simulations, and Experimental Results
76(2)
4.2.3.1 ICEM Model Parameters Extraction
76(1)
4.2.3.2 Measurements and Simulations
77(1)
4.3 Overview of the 3D Interconnect and Substrate Modeling Approach
78(11)
4.3.1 The Different Steps of the Modeling Approach
78(16)
4.3.1.1 Compact Models of the Medium-TSV (and Coplanar Line)
79(2)
4.3.1.2 Global Electrical Context Modeling
81(1)
4.3.1.3 To a Simulation Platform
82(7)
4.4 Conclusion
89(2)
Acknowledgments
91(1)
References
91(2)
Chapter 5 Modeling of On-Chip Power Distribution Network 93(46)
Chulsoon Hwang
Jingook Kim
Jun Fan
Joungho Kim
James L. Drewniak
5.1 Introduction
93(1)
5.2 On-Chip Capacitors
94(5)
5.2.1 MOS Capacitor
94(2)
5.2.2 Through-Silicon Via
96(3)
5.3 On-Chip Interconnects
99(12)
5.3.1 Geometry and Equivalent Circuit
99(2)
5.3.2 Coplanar Waveguide Structure
101(4)
5.3.3 Microstrip
105(3)
5.3.4 Segmentation
108(3)
5.4 Off-Chip PDN Structures
111(4)
5.5 Power Supply-Induced Jitter (PSIJ)
115(19)
5.5.1 Analytical Approaches for PSIJ Modeling
115(5)
5.5.2 Analytical Derivations of PSIJ Transfer Function
120(7)
5.5.3 Extension to I/O Link BER Analysis
127(7)
References
134(5)
Chapter 6 Printed Circuit Board Integration of SoC Packages and Signal Integrity Issues at Board Level 139(56)
Norocel D. Codreanu
Ciprian Ionescu
6.1 SoC Packages for PCB and System Integration
139(3)
6.2 HDI and Embedded Components Technologies for SoC Packages and PCB
142(22)
6.2.1 Introduction
142(3)
6.2.2 Configurations of Integrated Passive Components
145(2)
6.2.3 Modeling and Simulation of Resistors at High Frequency
147(8)
6.2.4 Modeling Passive Components Using the Finite Element Methods (FEM)
155(4)
6.2.5 Modeling Embedded Inductors Using Closed Form Expressions
159(5)
6.3 Virtual Investigation Setup for Evaluation of SoC Based PCB Modules
164(8)
6.4 Investigations of PCB and Interconnection Elements
172(15)
6.5 Conclusions
187(2)
References
189(6)
Chapter 7 Modeling and Characterization of TSV-Induced Noise Coupling 195(38)
Xiao Sun
Martin Rack
Geert Van der Plas
Jean-Pierre Raskin
Eric Beyne
7.1 Introduction: Background and Driving Forces
196(1)
7.2 TSV Introduced EM Noise Coupling in 3D-ICs
197(11)
7.2.1 Equivalent Circuit Model of a TSV and Two Major Paths of Noise Coupling Introduced by TSVs
198(2)
7.2.2 Passive EM Coupling: TSV to TSV Noise Coupling
200(1)
7.2.3 Active EM Coupling: TSV to Planar and FinFET Transistor
201(4)
7.2.3.1 Test Structure Description and RF Measurements
201(1)
7.2.3.2 TSV-Planar nMOSFETs Noise Coupling
202(1)
7.2.3.3 TSV-nFinFETs Noise Coupling
202(2)
7.2.3.4 TSV-Active Device Coupling Mechanisms: Planar nMOSFETs versus nFinFETs
204(1)
7.2.4 Parasitic Surface Conduction
205(3)
7.2.4.1 Extension of the Depletion Capacitance along the Back-Side Passivation Layer
205(2)
7.2.4.2 BS Bridge Effect between Neighboring TSVs
207(1)
7.2.4.3 Discussion of Possible Solutions
208(1)
7.3 Coupling Mitigation Techniques and Signal Integrity
208(10)
7.3.1 Substrate Contact and Guard Ring
209(4)
7.3.1.1 Coupling Reduction of GR and Importance of TSV Pitch to Height Ratio
209(3)
7.3.1.2 TSV Driver and Load Impedances
212(1)
7.3.2 Ground Shielding TSVs
213(5)
7.3.2.1 Coupling in Large TSV Arrays
214(1)
7.3.2.2 TSV Driver and Load Impedances
215(3)
7.4 Modeling and Simulation Methodologies
218(12)
7.4.1 HFSS (High Frequency Structure Simulators)
219(1)
7.4.2 3D Circuit Model
220(6)
7.4.2.1 3D Circuit Model Approach
220(3)
7.4.2.2 Model Validation and Power
223(1)
7.4.2.3 3D TSV Extended Circuit Model and Validation
223(3)
7.4.3 Finite-Element Semiconductor Simulators: Silvaco Atlas
226(1)
7.4.4 SYNOPSYS TCAD Modeling
227(8)
7.4.4.1 TCAD Model Calibration
227(1)
7.4.4.2 Impact of TSV Diameter and Liner Thickness on Noise Coupling
228(1)
7.4.4.3 Impact of TSV Height on Noise Coupling
228(1)
7.4.4.4 Impact of Substrate Contact Location on Noise Coupling
229(1)
7.5 Summary and Conclusions
230(1)
References
231(2)
Chapter 8 Layout Strategies for Substrate Crosstalk Reduction in Low Cost CMOS Processes 233(28)
Pedro Mendonca dos Santos
Luis Mendes
Joao Caldinhas Vaz
Henrique Quaresma
8.1 Introduction
233(2)
8.2 Isolation Techniques Overview
235(13)
8.2.1 Isolation Structures for Standard CMOS
236(3)
8.2.1.1 P-Type and N-Type Guard-Rings
236(1)
8.2.1.2 P-Sub Guard-Ring and Deep Trench Isolation
237(1)
8.2.1.3 N-Well and Deep n-Well
238(1)
8.2.1.4 Active Suppression
238(1)
8.2.2 Isolation Structures in Non-Standard CMOS
239(2)
8.2.2.1 Buried Dielectric Layer Isolation
239(1)
8.2.2.2 Through-silicon Via Isolation
239(1)
8.2.2.3 Particles Irradiation Isolation
240(1)
8.2.3 Noise Propagation through Substrate
241(5)
8.2.3.1 Substrate Characterization Structures
241(1)
8.2.3.2 Substrate DC Characterization
241(1)
8.2.3.3 Substrate AC Characterization
242(4)
8.2.4 Modeling Isolation Structures
246(2)
8.3 Isolation Techniques and Structures in Low-Cost CMOS Nodes
248(9)
8.3.1 The Design of Pseudo-Deep N-Wells
249(1)
8.3.2 High Frequency Characterization of Noise Isolation Structures
250(1)
8.3.3 P-Sub Guard Ring
251(2)
8.3.4 Effect of the Guard-Ring Width
253(2)
8.3.5 Effect of the Guard-Ring Distance to the Noise Receiver
255(2)
References
257(4)
Chapter 9 Wireless Communications System-on-Chip Substrate Noise Real Time Sensing 261(20)
Thomas Noulis
Stefanos Stefanou
Errikos Lourandakis
Panayotis Merakos
Yiannis Moisiadis
9.1 Introduction
261(2)
9.2 State of the Art and Related Work
263(2)
9.3 Substrate Noise Sensor
265(5)
9.4 Noise Aggressor Architecture
270(2)
9.5 Substrate Noise Sensing on a Wireless Communication SoC
272(4)
9.6 Summary
276(1)
Acknowledgments
277(1)
References
277(4)
Chapter 10 System-on-Chip Substrate Crosstalk Measurement Techniques 281(44)
Konstantinos Moustakas
Thomas Noulis
Stylianos Siskos
10.1 Introduction
282(1)
10.2 Substrate Noise Coupling Mechanism
283(7)
10.2.1 Noise Generation and Injection
284(4)
10.2.1.1 Capacitive Coupling of Interconnects and Passive Devices
284(1)
10.2.1.2 Coupling through Diffusion Capacitance
285(1)
10.2.1.3 Coupling though Substrate Contacts
286(1)
10.2.1.4 Noise Injection through Impact Ionization
286(1)
10.2.1.5 Noise Injection through Power Grid Fluctuations
287(1)
10.2.1.6 Noise Injection Example of a CMOS Inverter
287(1)
10.2.2 Noise Propagation though the Substrate
288(1)
10.2.3 Noise Reception and Impact
289(1)
10.3 Substrate Noise Measurement
290(30)
10.3.1 Overview of Substrate Crosstalk Measurement Techniques
290(3)
10.3.2 Substrate Noise Sensor Requirements
293(1)
10.3.3 Analysis and Simulation of Substrate Measuring Techniques
294(24)
10.3.3.1 Bulk-Driven NMOS Transistors
294(3)
10.3.3.2 Source Follower-Transconductor (SF+Gm) Sensor
297(2)
10.3.3.3 DC-Coupled PMOS Sensor
299(5)
10.3.3.4 Differential Amplifier Based Substrate Noise Sensor
304(6)
10.3.3.5 Subthreshold Biased Differential Amplifier Substrate Noise Sensor
310(3)
10.3.3.6 On-Chip Digitizer
313(5)
10.3.4 Comparison of the Simulated Designs
318(2)
Acknowledgment
320(2)
References
322(3)
Chapter 11 3D IC Floorplanning Based on Thermal Interactions 325(18)
Boris Vaisband
Eby G. Friedman
11.1 Introduction
325(2)
11.2 Thermal Interaction
327(2)
11.3 3D Floorplan Methodology
329(1)
11.3.1 Global Floorplan
330(1)
11.3.2 Local Floorplan
330(1)
11.4 Proposed Algorithm
330(2)
11.5 Evaluation Results
332(5)
11.5.1 Suite of MCNC Benchmark Circuits
333(2)
11.5.2 Temperature Evaluation Using COMSOL
335(1)
11.5.3 Heterogeneous 3D Systems
336(1)
11.6 Conclusions
337(1)
Acknowledgment
338(1)
Appendix 11.1
338(1)
References
339(4)
Chapter 12 A Unified Method for Calculating Parasitic Capacitive and Resistive Coupling in VLSI Circuits 343(1)
Alkis A. Hatzopoulos
Michael G. Dimopoulos
12.1 Introduction
343(2)
12.2 General Model Description
345(2)
12.3 RCCG Method Formulation
347(13)
12.3.1 Elementary Structures of the RCCG Method
352(4)
12.3.2 Implementation on Typical Cases
356(4)
12.3.2.1 Coupling Capacitance
357(2)
12.3.2.2 Coupling Resistance between Two Contacts
359(1)
12.4 Substrate Resistance Extraction Method
360(5)
12.4.1 Substrate Resistance Extraction Algorithm
364(1)
12.5 RCCG Method Validation and Applications
365(4)
12.5.1 Measurement Results
366(2)
12.5.2 Simulation Results
368(1)
12.6 Experimental Results for the Resistance Extraction
369(3)
12.6.1 Simulation Results
369(1)
12.6.2 Measurement Results
370(2)
12.7 Summary
372(1)
References
373
Chapter 13 Coupling through Substrate for Millimeter Wave Frequencies 343(34)
Vasileios A. Gerakis
Alkis A. Hatzopoulos
13.1 Introduction
377(1)
13.2 Interconnections Coupling through Substrate
378(3)
13.3 Inductors Coupling through Substrate
381(5)
13.4 Guard Rings
386(7)
13.5 Shields
393(4)
13.6 Conclusions
397(1)
References
398
Chapter 14 Paradigm Shift of On-Chip Interconnects from Electrical to Optical 377(68)
Swati Joshi
Amit Kumar
Brajesh Kumar Kaushik
14.1 Introduction
402(1)
14.2 On-Chip Electrical Interconnects
403(1)
14.3 Issues with Electrical Interconnects
404(8)
14.3.1 Scaling of Electrical Interconnects
404(2)
14.3.2 Aspect-Ratio Limit
406(1)
14.3.3 Scattering
407(1)
14.3.4 Electromigration
407(2)
14.3.5 Reliability Issues with Low-K Dielectric Material
409(1)
14.3.6 Signal Integrity (Impedance Matching, Crosstalk, and Electromagnetic Interference)
410(1)
14.3.7 Synchronization Problem
411(1)
14.3.8 Power Dissipation
411(1)
14.4 Conventional On-Chip Interconnects
412(4)
14.4.1 Carbon Nanotubes (CNTs)
413(1)
14.4.2 Graphene Nanoribbons (GNRs)
414(2)
14.5 On-Chip Optical Interconnects
416(1)
14.6 Benefits of Optical Interconnects
416(2)
14.7 Optical Communication Link
418(16)
14.7.1 Optical Sources
419(2)
14.7.1.1 Device Requirements
421(1)
14.7.2 Waveguides
421(3)
14.7.3 Passive Devices
424(5)
14.7.3.1 Directional Coupler
424(1)
14.7.3.2 Tapers
425(1)
14.7.3.3 Multimode Interference Coupler (MMI)
426(1)
14.7.3.4 Y-Junction
427(1)
14.7.3.5 Mach-Zehnder Interferometer (MZI)
427(1)
14.7.3.6 Ring Resonator
427(1)
14.7.3.7 Arrayed Waveguide Gratings (AWG)
428(1)
14.7.3.8 Diffraction Grating
429(1)
14.7.4 Optical Modulators in Silicon Photonic Circuits
429(3)
14.7.4.1 Basic Modulator Structures
431(1)
14.7.5 Photodetectors
432(6)
14.7.5.1 Photo Detector Electrical Structures
433(1)
14.7.5.2 Requirements
434(1)
14.8 Wavelength Division Multiplexing
434(1)
14.9 Performance Comparison between Electrical and Optical Interconnect
435(3)
14.10 Challenges with Optical Interconnects
438(2)
14.10.1 Recent Advancement in Graphene-Based Optical Interconnects
439(1)
References
440(5)
Chapter 15 Electro-Thermal Considerations Dedicated to 3D Integration; Noise Coupling 445(40)
Yue Ma
Olivier Valorge
J.R. Cardenas-Valdez
J.C. Nunez-Perez
J. Verdier
Francis Calmon
Christian Gontrand
15.1 Introduction
446(2)
15.2 Mathematical Tools
448(7)
15.2.1 Green Kernels
448(1)
15.2.2 Substrate Analysis
449(2)
15.2.3 Transmission Line Analogy for Multilayered Media
451(2)
15.2.4 Comparison Results with Fern Method
453(2)
15.2.4.1 Model via-Contact
453(2)
15.3 Modeling Approach Validation and Test Structures' RF Behaviors
455(7)
15.3.1 The Simulation Platform
456(1)
15.3.2 Study of Signal Integrity in TSV Matrices
456(6)
15.4 Heat Equation
462(5)
15.4.1 Boundary Conditions
464(3)
15.5 3D Electrical Noise Approach
467(3)
15.6 Digital Perturbations
470(11)
15.6.1 Methodology
471(8)
15.6.2 Numerical Experiences and Discussion
479(2)
15.7 Conclusion
481(1)
Acknowledgment
482(1)
References
482(3)
Index 485
Thomas Noulis is an Assistant Professor in the Physics Department at Aristotle University, in the Electronics Laboratory. From 2012 to 2015, he worked with INTEL Corp., as a Staff RFMS Engineer, in the Mobile & Communications Group in Munich-Germany, where he specialized on 14nm & 28nm design, modeling/characterization, crosstalk and in SoC product active area minimization & migration. Before joining INTEL, from May 2008 to March 2012, Dr. Noulis was with HELIC Inc, initially as Analog/RF IC designer and then as an R&D Engineer specializing in substrate coupling, signal and noise integrity and analog/RFIC design. Thomas Noulis holds a B.Sc. Degree in Physics (2003), a M.Sc. Degree in Electronics Engineering (2005), and a Ph.D in the "Design of signal processing integrated circuits" (2009) from Aristotle Univ. of Thessaloniki, Greece and in collaboration with LAAS (Toulouse-France). From 2004 to 2009, he participated as a principal researcher in multiple European and National research projects related to Space Application and Nuclear Spectroscopy IC design; simultaneously, from 2004 to 2010, he also collaborated as a Visiting/Adjunct Professor with Universities and Technical Institutes. Dr. Noulis is the main author of more than 40 publications, in journals, conferences and scientific book chapters. He holds one French and World patent. His work received more than 50 citations. He is an active reviewer of multiple international journals and has given multiple invited presentations in European Research Institutes on crosstalk and Rad-IC design. Dr. Noulis has been awarded for his research activity by conferences and research organizations and can be reached at t.noulis@gmail.com.
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