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Network Topologies, Models, and Applications |
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1 | (37) |
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1 | (7) |
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8 | (15) |
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10 | (1) |
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General Run Time Optimizations |
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10 | (2) |
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12 | (1) |
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13 | (1) |
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14 | (9) |
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23 | (14) |
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Parallel Communication Models |
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23 | (4) |
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Parallel Computation Models |
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27 | (1) |
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Program Locality and Latency Hiding |
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28 | (3) |
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Customization of Interconnection Networks |
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31 | (2) |
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33 | (1) |
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34 | (1) |
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35 | (1) |
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35 | (2) |
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37 | (58) |
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37 | (22) |
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37 | (2) |
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Virtual Circuits - Flow Control |
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39 | (2) |
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41 | (1) |
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42 | (3) |
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Deadlock, Livelock, and Starvation |
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45 | (5) |
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Fault Tolerance, Reliability, and Diagnosis Models |
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50 | (9) |
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59 | (11) |
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60 | (1) |
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61 | (4) |
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65 | (1) |
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Other Communication Patterns |
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65 | (1) |
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66 | (3) |
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Reduction of Communication Problems |
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69 | (1) |
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Routing in General Graphs |
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70 | (10) |
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Performance of Routing Algorithms |
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70 | (7) |
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77 | (1) |
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PRAM Emulation on Distributed Memory |
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78 | (1) |
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Optimality and Lower Bounds |
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79 | (1) |
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Performance of Packet Routers |
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80 | (15) |
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Continuous Routing Models |
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82 | (1) |
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83 | (1) |
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Split Input Buffered Switch |
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84 | (2) |
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86 | (1) |
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87 | (1) |
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Performance Comparisons for Generic Switches |
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88 | (4) |
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Large Routers and Networks |
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92 | (2) |
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Technological Constraints - Cost vs. Performance |
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94 | (1) |
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Multistage Interconnection Networks |
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95 | (64) |
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95 | (2) |
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Representation and Functionalities of Multistage Networks |
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97 | (3) |
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Design and Classification of MINs |
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100 | (6) |
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106 | (15) |
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Shuffle-Exchange and Omega Network |
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106 | (3) |
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109 | (1) |
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Inverse Omega, Baseline, Indirect Cube, etc. |
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110 | (5) |
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MIN Performance - Static and Dynamic Patterns |
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115 | (1) |
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Permutation Capability - Static Traffic |
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115 | (2) |
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Bandwidth and Latency - Dynamic Traffic |
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117 | (4) |
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Permutation and Nonblocking Networks |
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121 | (9) |
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Benes Permutation Network |
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121 | (4) |
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Other Permutation Networks |
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125 | (1) |
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The Clos Family of Networks |
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125 | (4) |
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Other Nonblocking Networks |
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129 | (1) |
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130 | (5) |
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Fault Tolerance, Reliability, and Diagnosis |
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135 | (7) |
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Fault Tolerance and Reliability |
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135 | (5) |
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140 | (2) |
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142 | (12) |
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142 | (6) |
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148 | (4) |
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152 | (1) |
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Balancing and Counting Networks |
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152 | (2) |
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Interconnection Networks in Cryptology |
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154 | (1) |
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154 | (1) |
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VLSI Layout and Customization |
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155 | (1) |
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Commercial Multistage Systems |
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155 | (4) |
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159 | (48) |
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159 | (5) |
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Hypercube Communication and Sorting |
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164 | (27) |
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Online Permutation Routing |
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164 | (5) |
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Offline Permutation Routing |
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169 | (2) |
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171 | (3) |
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174 | (3) |
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Global Communications with Linear Model |
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177 | (4) |
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181 | (1) |
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182 | (8) |
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Cut-Through, Wormhole, Circuit Switching, and Hot-Potato Routing |
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190 | (1) |
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Hypercube Embeddings and Algorithms |
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191 | (5) |
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Allocation and Scheduling Strategies |
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196 | (6) |
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VLSI Layout and Customization |
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202 | (2) |
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Commercial Hypercube Systems |
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204 | (3) |
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207 | (74) |
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207 | (8) |
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209 | (2) |
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211 | (1) |
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212 | (2) |
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214 | (1) |
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214 | (1) |
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215 | (15) |
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Lower Bounds for Routing and Sorting on Arrays |
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216 | (1) |
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217 | (4) |
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221 | (1) |
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222 | (6) |
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228 | (2) |
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230 | (38) |
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230 | (16) |
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246 | (1) |
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247 | (1) |
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248 | (2) |
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Cut-Through - Wormhole - Hot-Potato Routing |
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250 | (2) |
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1-1 and k-k Sorting Algorithms |
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252 | (15) |
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Global Communications and Algorithms |
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267 | (1) |
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268 | (6) |
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Higher Dimensional Arrays |
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268 | (1) |
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269 | (4) |
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273 | (1) |
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273 | (1) |
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Allocation and Scheduling Strategies |
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274 | (2) |
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VLSI Layout and Customization |
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276 | (1) |
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276 | (5) |
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281 | (38) |
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282 | (15) |
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Shuffle-Exchange Digraphs |
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297 | (5) |
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302 | (6) |
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308 | (9) |
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317 | (2) |
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Future Trends in Parallel Communication |
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319 | (6) |
Bibliography |
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325 | (58) |
Index |
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383 | |