Muutke küpsiste eelistusi

E-raamat: Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard

,
Teised raamatud teemal:
  • Formaat - PDF+DRM
  • Hind: 110,53 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test StandardSuurem pilt
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

This book focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the very large scale integrated (VLSI) design flow. After a survey of existing techniques for power constrained testing of VLSI circuits, several test automation techniques are presented for reducing power in scan-based sequential circuits and BIST data paths. Nicolici is affiliated with McMaster University, Canada. Al-Hashimi is affiliated with the University of Southampton, UK. Annotation (c) Book News, Inc., Portland, OR (booknews.com)

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.
Foreword v
Preface ix
Acknowledgments xi
Design and Test of Digital Integrated Circuits
1(20)
Introduction
1(1)
VLSI Design Flow
2(2)
External Testing Using Automatic Test Equipment
4(3)
Internal Testing Using Built-In Self-Test
7(10)
Power Dissipation During Test Application
17(2)
Organization of the Book
19(2)
Power Dissipation During Test
21(10)
Introduction
21(1)
Test Power Modeling and Preliminaries
22(3)
Power Concerns During Test
25(1)
Sources of Higher Power Dissipation During Test Application
26(4)
Summary
30(1)
Approaches to Handle Test Power
31(20)
Introduction
31(1)
A Taxonomy of the Existing Approaches for Power-Constrained Testing
31(3)
Test Set Dependent vs. Test Set Independent Approaches
34(3)
Test-per-Clock vs. Test-per-Scan
37(1)
Internal Test vs. External Test
38(8)
Single vs. Multiple Test Sources and Sinks
46(1)
Power-Constrained Test Scheduling
46(3)
Summary
49(2)
Best Primary Input Change Time
51(36)
Introduction
51(1)
Scan Cell and Test Vector Reordering
52(3)
A Technique for Power Minimization
55(13)
Algorithms for Power Minimization
68(5)
Experimental Results
73(12)
Summary
85(2)
Multiple Scan Chains
87(26)
Introduction
87(1)
Multiple Scan Chain-Based DFT Architecture
88(9)
Multiple Scan Chains Generation
97(7)
Experimental Results
104(7)
Summary
111(2)
Power-Conscious Test Synthesis and Scheduling
113(26)
Introduction
113(2)
Power Dissipation in BIST Data Paths
115(2)
Effect of Test Synthesis and Scheduling
117(7)
Power-Conscious Test Synthesis and Scheduling Algorithm
124(8)
Experimental Results
132(5)
Summary
137(2)
Power Profile Manipulation
139(20)
Introduction
139(1)
The Global Peak Power Approximation Model
139(2)
Power Profile Manipulation
141(6)
Power-Constrained Test Scheduling
147(6)
Experimental Results
153(3)
Summary
156(3)
Conclusion
159(4)
References 163(12)
About the Authors 175(2)
Index 177
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97803064873162e.html
Märksõnad: