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E-raamat: Power Microelectronics: Device And Process Technologies (Second Edition)

(Nus, S'pore), (Nus, S'pore), (Nat'l Tsing Hua Univ, Taiwan)
  • Formaat: 608 pages
  • Ilmumisaeg: 14-Mar-2017
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • Keel: eng
  • ISBN-13: 9789813200265
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Power Microelectronics: Device And Process Technologies (Second Edition)Suurem pilt
  • Formaat: 608 pages
  • Ilmumisaeg: 14-Mar-2017
  • Kirjastus: World Scientific Publishing Co Pte Ltd
  • Keel: eng
  • ISBN-13: 9789813200265
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"This is an excellent reference book for graduates or undergraduates studying semiconductor technology, or for working professionals who need a reference for detailed theory and working knowledge of processes in the field of power semiconductor devices."IEEE Electrical Insulation MagazineThis descriptive textbook provides a clear look at the theories and process technologies necessary for understanding the modern power semiconductor devices, i.e. from the fundamentals of p-n junction electrostatics, unipolar MOSFET and superjunction structures, bipolar IGBT, to the most recent wide bandgap SiC and GaN devices. It also covers their associated semiconductor process technologies. Real examples based on actual fabricated devices, with the process steps described in clear detail are especially useful. This book is suitable for university courses on power semiconductor or power electronic devices. Device designers and researchers will also find this book a good reference in their work, especially for those focusing on the advanced device development and design aspects.
Acknowledgement v
About the Authors vii
1 Introduction 1(6)
2 Carrier Physics and Junction Electrostatics 7(74)
2.1 Introduction
7(1)
2.2 Crystal Structure and Energy Bands
7(7)
2.3 Carrier Concentration and Fermi Level
14(7)
2.3.1 Intrinsic Semiconductor
17(1)
2.3.2 Extrinsic Semiconductor
18(3)
2.4 Carrier Transport
21(7)
2.4.1 Carrier Drift
22(4)
2.4.2 Carrier Diffusion
26(2)
2.4.3 Resistivity
28(1)
2.5 Bandgap Reduction
28(3)
2.6 Carrier Recombination
31(17)
2.6.1 Carrier Lifetime
37(2)
2.6.2 Carrier Lifetime Control
39(6)
2.6.3 Auger Recombination
45(3)
2.7 Basic Equations in Semiconductor
48(2)
2.8 p-n Junction Electrostatics
50(4)
2.9 Junction Breakdown Phenomena
54(7)
2.9.1 Abrupt pt-n Junction
58(1)
2.9.2 Linearly Graded Junction
59(2)
2.10 Punchthrough Phenomenon
61(3)
2.11 Junction Termination
64(12)
2.11.1 Cylindrical Junction
65(3)
2.11.2 Spherical Junction
68(1)
2.11.3 Floating Field Ring
68(2)
2.11.4 Etched Contour Termination
70(1)
2.11.5 Bevelled Edge Termination
71(2)
2.11.6 Field Plate
73(1)
2.11.7 Junction Termination Extension
74(1)
2.11.8 SIPOS (Semi-insulating Polycrystalline Silicon) Termination
75(1)
2.12 Summary
76(1)
References
76(5)
3 Bipolar Junction Diode 81(62)
3.1 Introduction
81(2)
3.2 Basic Junction Diode Theory
83(7)
3.2.1 Forward Conduction
83(3)
3.2.2 Short-Base Diode
86(1)
3.2.3 Junction Capacitance
87(3)
3.3 High-Voltage p+-n- -n+ Diode
90(15)
3.3.1 Forward Conduction
91(7)
3.3.2 Reverse Blocking
98(1)
3.3.3 Temperature Effect
99(6)
3.4 Schottky Barrier Diode
105(8)
3.4.1 Forward Conduction
107(3)
3.4.2 Reverse Blocking
110(3)
3.5 Ohmic Contact
113(3)
3.6 GaAs and SiC Power Diodes
116(5)
3.7 Switching Characteristics
121(7)
3.7.1 Turn-on Transient
122(2)
3.7.2 Turn-off Transient
124(4)
3.8 MPS (Merged p-i-n/Schottky) Diode
128(2)
3.9 Smart-Power Integrated Synchronous Rectifier
130(8)
3.10 Summary
138(1)
References
138(5)
4 Power Metal-Oxide-Semiconductor Field-Effect Transistor 143(48)
4.1 Introduction
143(1)
4.2 Basic MOS Physics
144(8)
4.2.1 Flat-Band State
146(1)
4.2.2 Accumulation State
146(1)
4.2.3 Depletion State
146(1)
4.2.4 Inversion State
147(2)
4.2.5 MOS Capacitance
149(2)
4.2.6 Threshold Voltage
151(1)
4.3 Static Characteristics
152(8)
4.3.1 Linear Region Operation
154(4)
4.3.2 Saturation Region Operation
158(1)
4.3.3 Mobility Degradation
159(1)
4.3.4 Forward Blocking
160(1)
4.4 Switching Characteristics
160(8)
4.4.1 Turn-on Transient
161(2)
4.4.2 Turn-off Transient
163(3)
4.4.3 Gate Charge
166(1)
4.4.4 High-Frequency Operation
167(1)
4.4.5 Parasitic Body Diode
168(1)
4.5 dv/dt Limit
168(2)
4.6 Dummy-Gated Structure
170(2)
4.7 Folded Gate Structure
172(1)
4.8 Lateral Radio Frequency (RF) Power MOSFET
173(8)
4.8.1 Graded Gate
174(1)
4.8.2 Stepped Lateral Double Diffusion
175(1)
4.8.3 Partial Silicon-on-Insulator Platform
175(2)
4.8.4 Partial SOI Platform Formation
177(4)
4.9 Parallel and Series Operations
181(2)
4.10 Gate Drive Circuits
183(3)
References
186(5)
5 Insulated-Gate Bipolar Transistor 191(58)
5.1 Introduction
191(2)
5.2 Device Structure and Current-Voltage Characteristics
193(6)
5.2.1 Forward Conduction Characteristics
195(4)
5.2.2 Output Resistance
199(1)
5.3 Switching Characteristics
199(2)
5.4 Latch-up
201(4)
5.5 Temperature Effects
205(1)
5.6 Series and Parallel Operations
206(1)
5.7 Device Operations under Soft Switching
207(3)
5.7.1 Dual-Gate IGBT for ZV Soft Switching
208(2)
5.8 Lateral IGBT Structure
210(2)
5.9 Integrated Current Sensor
212(8)
5.9.1 Fabrication Aspects
216(1)
5.9.2 Performances
217(3)
5.10 Safe Operating Area
220(3)
5.11 Overcurrent Protection
223(7)
5.12 Vertical IGBT Fabrication Process
230(1)
5.13 Related MOS-Bipolar Structures
231(13)
5.13.1 Emitter Switched Thyristor (EST)
231(6)
5.13.2 Base-Resistance-Controlled Thyristor (BRT)
237(5)
5.13.3 Injection-Enhanced Insulated-Gate Bipolar Transistor (IEGT)
242(1)
5.13.4 MOS-Controlled Thyristor (MCT)
243(1)
References
244(5)
6 Superjunction Structures 249(60)
6.1 Introduction
249(1)
6.2 The Unipolar Ideal Silicon Limit
250(3)
6.3 The Superjunction Structure
253(10)
6.3.1 SJ Electric Field Profiles
255(4)
6.3.2 Charge Imbalance
259(2)
6.3.3 Fabrication Technologies
261(2)
6.4 Practical SJ Performance
263(13)
6.4.1 The Practical Concentration Equation
274(1)
6.4.2 Practical SJ Performance Equation
275(1)
6.5 Polysilicon Flanked VDMOS (PF VDMOS)
276(4)
6.6 Oxide Bypassed (OB) SJ MOSFET
280(8)
6.7 Graded Doping in Drift Region
288(1)
6.8 Tunable Oxide Bypassed MOSFETs
289(7)
6.9 Gradient Oxide Bypassed (GOB) Structure
296(4)
6.10 Lateral Superjunction Power MOSFET
300(5)
6.10.1 Device Process Technology
303(2)
References
305(4)
7 Silicon Carbide Power Devices 309(50)
7.1 Introduction
309(1)
7.2 SiC Material Properties and Processing Technologies
310(9)
7.2.1 Material Properties
311(3)
7.2.2 Processing Technologies
314(5)
7.3 High Voltage Designs for SiC Devices
319(5)
7.3.1 Drift Region and Ideal Breakdown Voltage
319(2)
7.3.2 Edge Termination for SiC Power Devices
321(3)
7.4 SiC Rectifiers
324(5)
7.4.1 SiC Schottky Barrier Diodes
324(3)
7.4.2 SiC PIN Diodes
327(2)
7.5 SiC Unipolar Switches
329(12)
7.5.1 SiC MOSFETs
329(10)
7.5.2 SiC JFETs
339(2)
7.6 SiC Bipolar Switches
341(6)
7.6.1 SiC BJTs and Thyristors
342(4)
7.6.2 SiC IGBTs
346(1)
7.7 SiC Lateral Devices
347(2)
References
349(10)
8 Gallium Nitride Power Devices 359(64)
8.1 Introduction
359(2)
8.2 AlGaN/GaN and InGaN/GaN Heterojunction Configurations
361(11)
8.2.1 Theoretical Calculations of Polarization Effects
361(6)
8.2.2 Calculation of 2DEG Sheet Carrier Density
367(3)
8.2.3 Calculation of Critical Thickness of Strained Layer
370(2)
8.3 Simulation of GaN HEMTs
372(6)
8.3.1 Fabrication Induced Trap Charges
372(3)
8.3.2 Normally-off HEMT Device with Field Plates
375(3)
8.4 Current Collapse in GaN HEMT
378(11)
8.5 Reduction of Current Collapse with Gate Field Plate
389(3)
8.6 Temperature Effects
392(1)
8.7 Normally-off Operations in AlGaN/GaN HEMTs
393(6)
8.8 High Threshold Voltage Normally-off MIS-HEMTs
399(6)
8.9 Argon Pre-processed Fluorination Plasma Treatment
405(5)
8.10 High Temperature Threshold Voltage Stability
410(5)
8.11 GaN-Based Inverter Configuration
415(4)
8.12 Summary
419(1)
References
420(3)
9 Fabrication and Modeling of Power Devices 423(28)
9.1 Unit Process Steps
423(16)
9.1.1 Lithography
423(3)
9.1.2 Etching
426(1)
9.1.3 Deposition
427(2)
9.1.4 Oxidation
429(3)
9.1.5 Ion Implantation
432(4)
9.1.6 Epitaxy
436(1)
9.1.7 Diffusion
436(3)
9.2 Basic Models for the Simulation of Unit Process Steps
439(6)
9.2.1 Thermal Oxidation Models
439(2)
9.2.2 Diffusion Models
441(1)
9.2.3 Ion Implantation Models
442(1)
9.2.4 Optical Lithography
443(1)
9.2.5 Etching
444(1)
9.2.6 Deposition
445(1)
9.3 Advances in the Processes for Power Devices
445(5)
9.3.1 Modifications to Improve Gate Oxide Reliability and Breakdown Performance
445(2)
9.3.2 Use of Selective Epitaxial Growth for Performance Enhancement
447(3)
References
450(1)
10 Practical Case Studies in Silicon Power Devices 451(70)
10.1 Case Study I: Process Integration and Design of PFVDMOS
451(32)
10.1.1 Process Integration to Implement PFVDMOS Device
452(3)
10.1.2 Simulation and Process Parameter Determination of PFVDMOS Device
455(13)
10.1.3 Experimental Results
468(15)
10.2 Case Study II: Tunable Oxide Bypass MOSFETS
483(35)
10.2.1 100 V TOBUMOS Fabrication
484(1)
10.2.2 Simulation on 100 V TOBUMOS
485(2)
10.2.3 Process Flow and Cross-Sections
487(9)
10.2.4 Key Precautions in TOBUMOS Fabrication
496(4)
10.2.5 Device Structure and Mask Layout Design
500(3)
10.2.6 Mask Floorplan and Splits for 100 V TOBUMOS Fabrication
503(2)
10.2.7 100 V TOBUMOS Measurement Results and Discussions
505(5)
10.2.8 Investigations for Off State Failure
510(6)
10.2.9 Measurement Results on New Modified TOBUMOS Fabrication
516(2)
References
518(3)
11 Practical Case Studies in Wide Bandgap Power Devices 521(66)
11.1 Case Study I: Process Integration and Design of SiC DIMOSFET
521(28)
11.1.1 Process Integration to Self-Aligned SiC DIMOSFET
521(2)
11.1.2 Simulation of a Cell Structure for a Self-Aligned SiC DIMOSFET
523(15)
11.1.3 Experimental Results
538(11)
11.2 Case Study II: Design of Normally-off GaN HEMT for Power Electronics Applications
549(33)
11.2.1 Fabrication of Partial AlGaN recess Metal-Insulator-Semiconductor (MIS) HEMT
550(5)
11.2.2 Innovative Normally-off (MIS) HEMT Structure Using Multi-fluorinated Gate Stack
555(3)
11.2.3 Obtaining Normally-off (MIS) HEMT Structure Capable of Operating at High Temperature Using Ar and Single F-Treatment
558(24)
11.2.4 Concluding Remarks
582(1)
References
582(5)
Index 587
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