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E-raamat: Power and Performance: Software Analysis and Optimization

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(Software engineer, Intels Open Source Technology Center, Hillsboro, OR, USA)
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 27-Apr-2015
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780128008140
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Power and Performance: Software Analysis and OptimizationSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 27-Apr-2015
  • Kirjastus: Morgan Kaufmann Publishers In
  • Keel: eng
  • ISBN-13: 9780128008140
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Power and Performance in Enterprise Systems is a guide to solving performance problems in modern systems. Power efficient chips are no help if the software those chips run on is inefficient. Starting with the necessary architectural background as a foundation, the book demonstrates the proper usage of performance analysis tools in order to pinpoint the cause of performance problems, and includes best practices for handling common performance issues those tools identify.

  • Provides expert perspective from a key member of Intel’s optimization team on how processors and memory systems influence performance
  • Presents ideas to improve architectures running mobile, desktop, or enterprise platforms
  • Demonstrates best practices for designing experiments and benchmarking throughout the software lifecycle
  • Explains the importance of profiling and measurement to determine the source of performance issues

Arvustused

"...covers the intended topics with enough clarity and depth to serve both as a potential textbook and as a reference for practitionersThis one of the best technical books I have read in a while."--Computing Reviews

Muu info

Intel insider's guide to enabling performance in modern system architectures
Introduction xiii
PART 1 BACKGROUND KNOWLEDGE
Chapter 1 Early Intel® Architecture
3(28)
1.1 Intel® 8086
5(11)
1.1.1 System State
7(1)
1.1.2 Registers
8(2)
1.1.3 Instructions
10(3)
1.1.4 Machine Code Format
13(3)
1.2 Intel® 8087
16(4)
1.2.1 IEEE 754 Floating Point
16(3)
1.2.2 x87 Floating Point
19(1)
1.3 Intel® 80286 and 80287
20(3)
1.3.1 Protected and Real Mode
21(1)
1.3.2 Protected Mode Segmentation
21(1)
1.3.3 Task Control
22(1)
1.4 Intel® 80386 and 80387
23(8)
1.4.1 32-Bit Mode
24(2)
1.4.2 Paging
26(2)
References
28(3)
Chapter 2 Intel® Pentium® processors
31(12)
2.1 Intel® Pentium®
32(2)
2.1.1 Superscalar
33(1)
2.2 Intel® Pentium® Pro
34(4)
2.2.1 PAE
34(1)
2.2.2 μops
35(1)
2.2.3 Out-of-Order Execution
36(2)
2.3 Intel® Pentium® 4
38(5)
2.3.1 IA-32eMode
38(2)
2.3.2 Multi-Core
40(1)
2.3.3 Intel® Hyper-Threading
41(1)
References
41(2)
Chapter 3 Intel® Core™ processors
43(10)
3.1 Intel® Pentium® M
44(4)
3.1.1 ACPI
44(4)
3.2 Second Generation Intel® Core™ Processor Family
48(5)
3.2.1 Intel® HD Graphics
49(1)
3.2.2 Intel® Flex Memory Technology
49(1)
3.2.3 Intel® Turbo Boost Technology
50(1)
3.2.4 Intel® RAPL
51(1)
References
52(1)
Chapter 4 Performance Workflow
53(20)
4.1 Step 0: Defining the Problem
54(2)
4.2 Step 1: Determine the Source of the Problem
56(1)
4.3 Step 2: Determine Whether the Bottleneck Can Be Avoided
57(1)
4.4 Step 3: Design a Reproducible Experiment
57(2)
4.5 Step 4: Check Upstream
59(8)
4.5.1 Who
60(1)
4.5.2 Where and How
60(2)
4.5.3 What
62(5)
4.6 Step 5: Algorithmic Improvement
67(1)
4.7 Step 6: Architectural Tuning
68(2)
4.8 Step 7: Testing
70(1)
4.9 Step 8: Performance Regression Testing
71(2)
References
71(2)
Chapter 5 Designing Experiments
73(32)
5.1 Choosing a Metric
74(1)
5.2 Dealing with External Variables
74(5)
5.2.1 Controllable External Variables
74(3)
5.2.2 Uncontrollable External Variables
77(2)
5.3 Timing
79(6)
5.3.1 CPU Cycles
80(2)
5.3.2 Clock Time and Unix Time
82(3)
5.4 Phoronix Test Suite
85(20)
5.4.1 Running Phoronix
87(7)
5.4.2 Working with Results
94(1)
5.4.3 Creating Custom Tests
95(3)
5.4.4 Phoronix Resources
98(2)
References
100(5)
PART 2 MONITORS
Chapter 6 Introduction to Profiling
105(14)
6.1 PMU
106(4)
6.1.1 Event Counters
107(2)
6.1.2 Using Event Counters
109(1)
6.2 Top-Down Hierarchical Analysis
110(9)
6.2.1 Front End Bound
112(2)
6.2.2 Back End Bound
114(3)
6.2.3 Bad Speculation
117(1)
6.2.4 Retire
117(1)
References
118(1)
Chapter 7 Intel® VTune™ Amplifier XE
119(18)
7.1 Installation and Configuration
120(4)
7.1.1 Building the Kernel Modules
121(1)
7.1.2 System Configuration
122(2)
7.2 Data Collection and Reporting
124(13)
7.2.1 Collect Action
125(4)
7.2.2 Finalize Action
129(1)
7.2.3 Report Action
129(6)
References
135(2)
Chapter 8 Perf
137(30)
8.1 Event Infrastructure
138(20)
8.1.1 perf_event_open(2)
138(1)
8.1.2 Selecting an Event
139(5)
8.1.3 Measurement Parameters
144(3)
8.1.4 Enabling, Disabling, and Resetting Counters
147(1)
8.1.5 Reading Counting Events
148(4)
8.1.6 Reading Sampling Events
152(6)
8.2 Perf Tool
158(9)
8.2.1 Expressing Events
158(2)
8.2.2 Perf Stat
160(1)
8.2.3 Perf Record, Perf Report, and Perf Top
160(3)
8.2.4 Perf Timechart
163(2)
References
165(2)
Chapter 9 Ftrace
167(12)
9.1 DebugFS
168(8)
9.1.1 Tracers
169(7)
9.2 Kernel Shark
176(3)
References
178(1)
Chapter 10 GPU Profiling Tools
179(12)
10.1 Traditional Graphics Stack
180(4)
10.1.1 X11
180(1)
10.1.2 Hardware and Low-Level Infrastructure: DRI
181(1)
10.1.3 Higher Level Software Infrastructure
182(2)
10.2 buGLe
184(3)
10.3 Apitrace
187(4)
References
189(2)
Chapter 11 Other Helpful Tools
191(16)
11.1 GNU Profiler
191(3)
11.2 Gcov
194(1)
11.3 PowerTOP
195(6)
11.3.1 Overview
196(1)
11.3.2 Idle Stats
197(1)
11.3.3 Frequency Stats
198(1)
11.3.4 Device Stats
199(1)
11.3.5 Tunables
199(2)
11.4 LatencyTOP
201(1)
11.5 Sysprof
202(5)
11.5.1 Collection
202(1)
References
203(4)
PART 3 OPTIMIZATION TECHNIQUES
Chapter 12 Toolchain Primer
207(34)
12.1 Compiler Flags
209(2)
12.2 ELF and the x86/x86_64 ABIs
211(7)
12.2.1 Relocations and PIC
212(4)
12.2.2 ABI
216(2)
12.3 CPU Dispatch
218(9)
12.3.1 Querying CPU Features
219(5)
12.3.2 Runtime Dispatching
224(3)
12.4 Coding Style
227(6)
12.4.1 Pointer Aliasing
227(3)
12.4.2 Using the Appropriate Types and Qualifiers
230(1)
12.4.3 Alignment
231(2)
12.4.4 Loop Unrolling
233(1)
12.5 x86 Unleashed
233(8)
12.5.1 Standalone Assembly
234(2)
12.5.2 Inline Assembly
236(1)
12.5.3 Compiler Intrinsics
237(1)
References
238(3)
Chapter 13 Branching
241(10)
13.1 Avoiding Branches
242(5)
13.1.1 Extra Work and Masking
243(2)
13.1.2 Combining and Rearranging Branches
245(2)
13.2 Improving Prediction
247(4)
13.2.1 Profile Guided Optimization
248(1)
References
249(2)
Chapter 14 Optimizing Cache Usage
251(12)
14.1 Processor Cache Organization
252(2)
14.1.1 Cache Lines
253(1)
14.2 Querying Cache Topology
254(4)
14.3 Prefetch
258(1)
14.4 Improving Locality
259(4)
References
261(2)
Chapter 15 Exploiting Parallelism
263(12)
15.1 SIMD
265(10)
15.1.1 SIMD Registers
266(3)
15.1.2 SIMD Operations
269(4)
References
273(2)
Chapter 16 Special Instructions
275(4)
16.1 Intel® Advanced Encryption Standard New Instructions (AES-NI)
275(1)
16.1.1 Further Reading
276(1)
16.2 PCLMUL-Packed Carry-Less Multiplication
276(1)
16.2.1 Further Reading
277(1)
16.3 CRC32
277(1)
16.3.1 Further Reading
277(1)
16.4 SSE4.2 String Functions
277(2)
16.4.1 Further Reading
278(1)
Index 279
Jim Kukunas began programming at a young age, teaching himself C and x86 assembly. He is an alumnus of Allegheny College with a degree in Computer Science. Today, he is a software engineer in Intel's Open Source Technology Center. As a performance optimization engineer on the core Linux kernel team, much of his work focuses on kernel space and user space performance optimizations. His efforts have enhanced many projects including the Linux kernel, Zlib, the Englightenment Foundation Libraries, Meego, Android, and many others.
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