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1 | (14) |
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1.1 Context and Motivation |
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1 | (5) |
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6 | (9) |
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7 | (8) |
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15 | (16) |
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2.1 Petri Nets and Interpreted Petri Nets |
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15 | (12) |
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2.2 Computational Complexity of Algorithms |
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27 | (4) |
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28 | (3) |
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3 Perfect Graphs and Comparability Graphs |
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31 | (18) |
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31 | (5) |
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36 | (2) |
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38 | (4) |
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3.4 Recognition and Coloring of Comparability Graphs |
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42 | (7) |
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3.4.1 Recognition of Comparability Graphs |
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42 | (3) |
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3.4.2 Coloring of Comparability Graphs |
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45 | (2) |
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47 | (2) |
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4 Hypergraphs and Exact Transversals |
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49 | (10) |
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4.1 Main Definitions and Properties of Hypergraphs |
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49 | (3) |
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4.2 Properties of C-Exact Hypergraphs |
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52 | (1) |
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4.3 Algorithms Related to C-Exact Hypergraphs |
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53 | (6) |
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56 | (3) |
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5 Analysis of Concurrent Control Systems |
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59 | (18) |
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5.1 State Equation and Place Invariants |
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59 | (5) |
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64 | (5) |
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5.3 Sequentiality Analysis |
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69 | (3) |
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5.4 Properties of Concurrency and Sequentiality Hypergraphs |
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72 | (5) |
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74 | (3) |
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6 Decomposition of Concurrent Control Systems |
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77 | (22) |
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6.1 SM-Decomposition Based on Place Invariants |
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78 | (7) |
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78 | (2) |
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80 | (5) |
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6.2 SM-Decomposition Based on Graph Theory |
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85 | (5) |
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85 | (2) |
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87 | (3) |
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6.3 SM-Decomposition Based on Hypergraph Theory |
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90 | (9) |
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90 | (1) |
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91 | (6) |
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97 | (2) |
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7 Prototyping of Concurrent Control Systems |
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99 | (18) |
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7.1 Prototyping Flow of the Concurrent Systems |
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99 | (4) |
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7.1.1 Specification by an Interpreted Petri Net |
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99 | (1) |
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7.1.2 Decomposition of the System |
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100 | (2) |
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7.1.3 Modeling of the Decomposed Modules |
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102 | (1) |
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7.1.4 Verification of the System |
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102 | (1) |
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7.1.5 Implementation of the System |
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103 | (1) |
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7.2 Prototyping of Integrated Concurrent Control Systems |
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103 | (14) |
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7.2.1 Specification by an Interpreted Petri Net |
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104 | (3) |
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7.2.2 Decomposition and Synchronization of the System |
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107 | (2) |
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7.2.3 Modeling of the Decomposed Modules as FSMs |
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109 | (3) |
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7.2.4 Verification of the System (Software Simulation) |
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112 | (1) |
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7.2.5 Implementation of the System |
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113 | (1) |
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113 | (4) |
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8 Modelling of Concurrent Systems in Hardware Languages |
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117 | (22) |
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8.1 Traditional Modelling of Concurrent Systems in Hardware Description Languages |
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117 | (11) |
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8.1.1 The Basic Assumptions |
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118 | (1) |
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8.1.2 Description of Transitions, Places, Outputs |
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118 | (2) |
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8.1.3 Description of Concurrency |
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120 | (2) |
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8.1.4 Description of Conflicts |
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122 | (2) |
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124 | (4) |
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8.2 Modelling of Concurrent Systems as a Composition of Sequential Automata |
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128 | (11) |
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8.2.1 Description of an FSM in Verilog |
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128 | (3) |
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131 | (5) |
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136 | (3) |
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9 Implementation of Concurrent Control Systems in FPGA |
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139 | (28) |
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9.1 Introduction to the Programmable Devices |
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139 | (2) |
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9.2 Field Programmable Gate Arrays |
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141 | (4) |
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9.3 Implementation of Concurrent Controllers in FPGA |
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145 | (1) |
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9.4 Partial Reconfiguration of Concurrent Controllers |
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146 | (21) |
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9.4.1 The Idea of Partial Reconfiguration of an FPGA |
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147 | (1) |
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9.4.2 Partial Reconfiguration of Concurrent Systems |
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148 | (1) |
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9.4.3 Static Partial Reconfiguration |
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149 | (5) |
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9.4.4 Dynamic Partial Reconfiguration |
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154 | (10) |
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164 | (3) |
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167 | (4) |
Index |
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171 | |