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E-raamat: Radiation-Tolerant Delta-Sigma Time-to-Digital Converters

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Radiation-Tolerant Delta-Sigma Time-to-Digital ConvertersSuurem pilt
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This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and  measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective.

 

·         Discusses important aspects of radiation-tolerant analog IC design, including realistic applications and radiation effects on ICs;

·         Demonstrates radiation-hardened-by-design techniques through a design-test-radiation assessment practice;

·         Describes a new type of Time-to-Digital (TDC) converter designed for radiation-tolerant application;

·         Explains the design and measurement of all functional blocks (e.g., bandgap reference, relaxation oscillator) in the TDC.
1 Introduction
1(14)
1.1 Tiny Chips, Big Physics
1(2)
1.2 Integrated Circuits for Space and Nuclear Instrumentation
3(4)
1.2.1 Microelectronic Circuits for Space Missions
3(1)
1.2.2 Electronics and Radiation Hardening in the Nuclear Industry
4(3)
1.3 The MYRRHA Reactor
7(1)
1.4 Light Detection and Ranging
8(5)
1.4.1 LIDAR Techniques
8(3)
1.4.2 Pulsed TOF Laser Range Finder
11(2)
1.5 Book Organization
13(2)
2 Background on Time-to-Digital Converters
15(10)
2.1 Introduction
15(1)
2.2 TDC Topologies
15(6)
2.2.1 Flash TDC
16(2)
2.2.2 Pipeline TDC
18(1)
2.2.3 Successive Approximation TDC
19(1)
2.2.4 GRO TDC
20(1)
2.3 Performance Measures
21(4)
2.3.1 Raw Resolution
21(1)
2.3.2 Single-Shot Precision
22(1)
2.3.3 Sampling Rate
22(1)
2.3.4 Bandwidth
22(1)
2.3.5 Effective Resolution
22(1)
2.3.6 SNDR and ENOB
23(1)
2.3.7 Dynamic Range
23(2)
3 Radiation Hardened by Design
25(14)
3.1 Introduction
25(1)
3.2 Radiation Effects in CMOS ICs
26(5)
3.2.1 TID Effects in MOS Devices
26(4)
3.2.2 TID Effects in Advanced CMOS Technologies
30(1)
3.2.3 Single Event Effects
30(1)
3.3 Radiation Hardened by Design
31(4)
3.3.1 System-Level Approach
32(1)
3.3.2 Circuit-Level Approach
33(1)
3.3.3 Device-Level Approach
34(1)
3.3.4 Layout-Level Approach
34(1)
3.4 Radiation Hardness Assurance Qualification
35(4)
4 Background on Time-to-Digital Converters
39(30)
4.1 Introduction
39(2)
4.2 Architecture of the 1-1-1 MASH ΔΣ TDC
41(5)
4.2.1 The First-Order Error-Feedback TDC
41(2)
4.2.2 High-Order Noise Shaping TDC
43(3)
4.3 Noise Analysis
46(5)
4.3.1 Timing Jitter
48(1)
4.3.2 Phase Skew
48(3)
4.4 Chip I: First Prototyping of the MASH ΔΣ TDC
51(7)
4.4.1 Circuit Description
51(3)
4.4.2 Experimental Results
54(4)
4.5 Chip II: The MASH ΔΣ TDC with Delay-Line-Assisted Calibration
58(6)
4.5.1 Delay-Line-Assisted Calibration
58(2)
4.5.2 Physical Implementation
60(2)
4.5.3 Measurement Results
62(2)
4.6 Radiation Assessment of the MASH ΔΣ TDC
64(3)
4.7 Conclusions
67(2)
5 Radiation Hardened Bandgap References
69(12)
5.1 Introduction
69(1)
5.2 Total Ionizing Dose Effects in CMOS Bandgap References
70(3)
5.2.1 CMOS Bandgap Reference with Sub-1-V Operation
70(1)
5.2.2 TID Effects in CMOS Diodes
71(2)
5.3 Radiation-Hardened Bandgap References
73(3)
5.3.1 DBLC Technique
73(2)
5.3.2 Circuit Description
75(1)
5.4 Experiment Results
76(4)
5.4.1 Pre-rad Measurement
76(1)
5.4.2 Gamma-Irradiation Experiment
76(4)
5.5 Conclusions
80(1)
6 Low-Jitter Relaxation Oscillators
81(24)
6.1 Introduction
81(1)
6.2 On-Chip Clock Generation
82(1)
6.3 Performance Measures on Clock References
83(2)
6.3.1 Clock Stability and Accuracy
83(1)
6.3.2 Phase Noise and Jitter
84(1)
6.4 An Short Review of Relaxation Oscillators
85(5)
6.4.1 Relaxation Oscillators as VCOs
85(2)
6.4.2 Clock Generation Using Relaxation Oscillators
87(1)
6.4.3 Low-Jitter Oscillator Design
88(2)
6.5 The Relaxation Oscillator with SC Integrated Error Feedback
90(11)
6.5.1 Phase Noise Optimization
90(4)
6.5.2 System Implementation
94(3)
6.5.3 Experiment Results
97(4)
6.6 Conclusions
101(4)
7 Conclusions
105(2)
References 107(6)
Index 113
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