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E-raamat: Real-Time Electromagnetic Transient Simulation of AC-DC Networks

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Explore a comprehensive and state-of-the-art presentation of real-time electromagnetic transient simulation technology by leaders in the field

Real-Time Electromagnetic Transient Simulation of AC-DC Networks delivers a detailed exposition of field programmable gate array (FPGA) hardware based real-time electromagnetic transient (EMT) emulation for all fundamental equipment used in AC-DC power grids. The book focuses specifically on detailed device-level models for their hardware realization in a massively parallel and deeply pipelined manner as well as decomposition techniques for emulating large systems.

Each chapter contains fundamental concepts, apparatus models, solution algorithms, and hardware emulation to assist the reader in understanding the material contained within. Case studies are peppered throughout the book, ranging from small didactic test circuits to realistically sized large-scale AC-DC grids.

The book also provides introductions to FPGA and hardware-in-the-loop (HIL) emulation procedures, and large-scale networks constructed by the foundational components described in earlier chapters. With a strong focus on high-voltage direct-current power transmission grid applications, Real-Time Electromagnetic Transient Simulation of AC-DC Networks covers both system-level and device-level mathematical models. Readers will also enjoy the inclusion of:

  • A thorough introduction to field programmable gate array technology, including the evolution of FPGAs, technology trends, hardware architectures, and programming tools
  • An exploration of classical power system components, e.g., linear and nonlinear passive power system components, transmission lines, power transformers, rotating machines, and protective relays
  • A comprehensive discussion of power semiconductor switches and converters, i.e., AC-DC and DC-DC converters, and specific power electronic apparatus such as DC circuit breakers
  • An examination of decomposition techniques used at the equipment-level as well as the large-scale system-level for real-time EMT emulation of AC-DC networks
  • Chapters that are supported by simulation results from well-defined test cases and the corresponding system parameters are provided in the Appendix

Perfect for graduate students and professional engineers studying or working in electrical power engineering, Real-Time Electromagnetic Transient Simulation of AC-DC Networks will also earn a place in the libraries of simulation specialists, senior modeling and simulation engineers, planning and design engineers, and system studies engineers.

About the Authors xix
Preface xxi
Acknowledgments xxv
List of Acronyms
xxvii
1 Field Programmable Gate Arrays
1(16)
1.1 Overview
1(5)
1.1.1 FPGA Hardware Architecture
2(1)
1.1.2 Configurable Logic Block
3(1)
1.1.3 Block RAM
4(1)
1.1.4 Digital Signal Processing Slice
4(2)
1.2 Multiprocessing System-on-Chip Architecture
6(1)
1.3 Communication
7(2)
1.4 HIL Emulation
9(7)
1.4.1 Vivado® High-Level Synthesis Tool
9(2)
1.4.2 Vivado® Top-Level Design
11(2)
1.4.3 Number Representation and Operations
13(1)
1.4.4 FPGA Design Schemes
14(1)
1.4.4.1 Pipeline Design Architecture
14(1)
1.4.4.2 Parallel Design Architecture
14(1)
1.4.5 FPGA Experiment
15(1)
1.5 Summary
16(1)
2 Hardware Emulation Building Blocks for Power System Components
17(62)
2.1 Overview
17(1)
2.2 Concept of HEBB
18(1)
2.3 Numerical Integration
18(2)
2.4 Linear Lumped Passive Elements
20(7)
2.4.1 Model Formulation
20(1)
2.4.1.1 Resistance!?
20(1)
2.4.1.2 Inductance!
20(2)
2.4.1.3 Capacitance C
22(1)
2.4.1.4 RL Branch
23(1)
2.4.1.5 LC Branch
23(1)
2.4.1.6 RLCG Branch
24(2)
2.4.2 Hardware Emulation of Linear Lumped Passive Elements
26(1)
2.5 Sources
27(3)
2.5.1 Hardware Emulation of Sources
28(2)
2.6 Switches
30(2)
2.6.1 Hardware Emulation of Switches
30(2)
2.7 Transmission Lines
32(22)
2.7.1 Traveling Waves
32(3)
2.7.2 Traveling Wave Model
35(1)
2.7.2.1 Modal Transformation
36(3)
2.7.3 Hardware Emulation of the TWM
39(1)
2.7.3.1 Transformation Unit
39(1)
2.7.3.2 Update Unit
39(2)
2.7.4 Frequency Dependent Line Model
41(5)
2.7.5 Hardware Emulation of FDLM
46(1)
2.7.5.1 Convolution Unit
46(1)
2.7.5.2 Update Unit
47(1)
2.7.6 Universal Line Model
48(1)
2.7.6.1 Frequency-Domain Formulation
48(1)
2.7.6.2 Time-Domain Formulation
49(2)
2.7.7 Hardware Emulation of the ULM
51(1)
2.7.7.1 Update x Unit
52(1)
2.7.7.2 Convolution Unit
52(2)
2.7.7.3 Interpolation Unit
54(1)
2.8 Network Solver
54(9)
2.8.1 Hardware Emulation of Network Solver
55(1)
2.8.2 Paralleled EMT Solution Algorithm
55(3)
2.8.3 MainControl Module
58(1)
2.8.4 Real-Time Emulation Case Study
59(4)
2.9 Nonlinear Elements: Iterative Real-Time EMT Solver
63(14)
2.9.1 Compensation Method
64(1)
2.9.2 Newton-Raphson Method
65(2)
2.9.3 Hardware Emulation of Nonlinear Solver
67(1)
2.9.3.1 Nonlinear Function Evaluation
68(1)
2.9.3.2 Parallel Calculation of J and F(ikm)
68(3)
2.9.3.3 Parallel Gauss-Jordan Elimination
71(1)
2.9.3.4 Computing vc
71(1)
2.9.4 Case Studies
71(6)
2.10 Summary
77(2)
3 Power Transformers
79(64)
3.1 Overview
79(1)
3.2 Nonlinear Admittance-Based Real-Time Transformer Model
80(20)
3.2.1 Linear Model Formulation
80(2)
3.2.2 Linear Module Hardware Design
82(2)
3.2.3 Inode Unit Module
84(1)
3.2.4 Nonlinear Model Solution
85(3)
3.2.4.1 Preisach Hysteresis Model
88(1)
3.2.4.2 Nonlinear Module Hardware Design
89(1)
3.2.5 Frequency-Dependent Eddy Current Model
90(1)
3.2.6 Hardware Emulation of Power Transformer
91(3)
3.2.7 Real-Time Emulation Case Studies
94(1)
3.2.7.1 Case I
94(5)
3.2.7.2 Case II
99(1)
3.3 Nonlinear Magnetic Equivalent Circuit Based Real-time Multi-Winding Transformer Model
100(23)
3.3.1 Topological ST EMT Model
102(1)
3.3.1.1 ST Operating Principle
102(1)
3.3.1.2 Tap-selection Algorithm
102(1)
3.3.1.3 High-Fidelity Nonlinear MEC-Based ST Model
102(5)
3.3.1.4 Iron Core Hysteresis and Eddy Currents
107(2)
3.3.2 High-Fidelity Nonlinear MEC-Based ST Hardware Emulation
109(1)
3.3.2.1 Network Transient Emulation with Embedded ST
109(3)
3.3.3 Real-Time Emulation Case Studies
112(1)
3.3.3.1 Finite Element Modeling and Validation
112(1)
3.3.3.2 Case Studies
112(11)
3.4 Real-Time Finite-Element Model of Power Transformer
123(18)
3.4.1 Magnetodynamic Problem Formulation
123(3)
3.4.1.1 Refined TLM Solution
126(4)
3.4.1.2 Field-Circuit Coupling
130(2)
3.4.2 Hardware Emulation of Finite Element Model
132(4)
3.4.3 Case Studies
136(1)
3.4.3.1 Results and Validation
137(3)
3.4.3.2 Speed-up and Scalability
140(1)
3.5 Summary
141(2)
4 Rotating Machines
143(50)
4.1 Overview
143(1)
4.2 Lumped Universal Machine (UM) Model
144(13)
4.2.1 UM Model Formulation
144(2)
4.2.2 Interfacing UM Model with Network
146(2)
4.2.3 UM HEBB
148(1)
4.2.3.1 Speed & Angle Unit
149(1)
4.2.3.2 FrmTran Unit
150(1)
4.2.3.3 Compidq0 Unit
151(6)
4.23 A Flux & Torque Unit
157(1)
4.2.3.5 Update & CompVc Unit
151(1)
4.2.4 Real-Time Emulation Case Study
152(2)
4.2.5 Overall Power System HEBB for Real-Time EMT Emulation
154(4)
4.3 General Framework for State-Space Electrical Machine Emulation
158(12)
4.3.1 FPGA Design Approaches for Electrical Machine Emulation
159(1)
4.3.2 State-Space Representation of Machine Models
160(1)
4.3.3 System Configuration on FPGA
161(1)
4.3.3.1 Number Representation
161(1)
4.3.3.2 Floating-Point Implementation by VHDL
162(5)
4.3.3.3 Fixed-Point Implementation by Schematic
167(3)
4.3 A Evaluation of Designed Architectures
170(8)
4.3.4.1 Real-Time Emulation Accuracy Assessment
170(1)
4.3.4.2 Off-line Validation
171(1)
4.3.4.3 Hardware Resource Utilization
172(2)
4.3.5 Real-Time Emulation Case Studies
174(1)
4.3.5.1 Case I: Induction Motor Transients
174(1)
4.3.5.2 Case II: Synchronous Generator Transients
174(2)
4.3.5.3 Case III: Line Start-Permanent Magnet Synchronous Motor Transients
176(1)
4.3.5.4 Case IV: DC Motor Transients
177(1)
4.4 Nonlinear Magnetic Equivalent Circuit Based Induction Machine Model
178(12)
4.4.1 Magnetic Circuit
179(2)
4.4.2 Interfacing of Magnetic and Electric Circuits
181(1)
4.4.3 Electric Circuit
182(1)
4.4.4 Nonlinear Solution of Detailed MEC
182(1)
4.4.5 Hardware Emulation of Nonlinear MEC
183(2)
4.4.5.1 Parallel Gauss-Jordan Elimination Unit
185(2)
4.4.5.2 Parallel Computational Unit for Residual Vector
187(1)
4.4.5.3 Nonlinear Evaluation Unit
187(1)
4.4.6 Evaluation of Real-Time Emulation of Induction Machine
187(3)
4.5 Summary
190(3)
5 Protective Relays
193(24)
5.1 Overview
193(2)
5.2 Hardware Emulation of Multifunction Protection System
195(14)
5.2.1 Signal Processing HEBB
196(1)
5.2.1.1 CORDIC HEBB
196(2)
5.2.1.2 Symmetrical Components HEBB
198(1)
5.2.1.3 DFT HEBB
198(1)
5.2.1.4 Zero-Crossing Detection HEBB
199(4)
5.2.2 Multifunction Protective System HEBB
203(1)
5.2.2.1 Fault Detection HEBB
203(2)
5.2.2.2 Directional Overcurrent Protection HEBB
205(1)
5.2.2.3 Over/Under Voltage Protection HEBB
205(1)
5.2.2.4 Distance Protection HEBB
205(4)
5.2.2.5 Under/Over Frequency Protection HEBB
209(1)
5.3 Test Setup and Real-Time Results
209(5)
5.3.1 Case I
210(3)
5.3.2 Case II
213(1)
5.4 Summary
214(3)
6 Adaptive Time-Stepping Based Real-Time EMT Emulation
217(36)
6.1 Overview
217(2)
6.2 Nonlinear Solution and Adaptive Time-Stepping Schemes
219(17)
6.2.1 Nonlinear Element Solution Methods
219(1)
6.2.1.1 Newton-Raphson Method
219(1)
6.2.1.2 Piecewise Linearization (PWL) Method
219(1)
6.2.1.3 Piecewise N-R Method
220(1)
6.2.2 Adaptive Time-Stepping Schemes
220(1)
6.2.2.1 Local Truncation Error Method
220(1)
6.2.2.2 Iteration Count Method
221(1)
6.2.2.3 DVDT or DIDT Method
221(1)
6.2.3 Combinations of Adaptive Time-Stepping Schemes
222(1)
6.2.3.1 Measurements and Restrictions for Real-Time Emulation
222(1)
6.2.4 Case Studies
223(1)
6.2.4.1 Diode Full-Bridge Circuit
224(1)
6.2.4.2 Power Transmission System
225(4)
6.2.4.3 FPGA Implementation
229(5)
6.2.4.4 Real-Time Emulation Results
234(2)
6.3 Adaptive Time-Stepping Universal Line Model and Universal Machine Model for Real-Time Hardware Emulation
236(16)
6.3.1 Subsystem-Based Adaptive Time-Stepping Scheme
237(1)
6.3.2 Adaptive Time-Stepping ULM and UM Models
238(1)
6.3.2.1 ULM Computation
238(4)
6.3.2.2 Universal Machine Model Computation
242(1)
6.3.3 Real-Time Emulation Case Study
243(1)
6.3.3.1 Hardware Implementation
243(3)
6.3.3.2 Latency and Hardware Resource Utilization
246(1)
6.3.4 Results and Validation
247(1)
6.3.4.1 Validation of the ULM Model
247(1)
6.3.4.2 Real-Time Emulation Results
248(4)
6.4 Summary
252(1)
7 Power Electronic Switches
253(48)
7.1 Overview
253(2)
7.2 IGBT/Diode Nonlinear Behavioral Model
255(15)
7.2.1 Power Diode
256(1)
7.2.1.1 Mathematical Model
256(1)
7.2.1.2 Hardware Module Architecture
257(2)
7.2.2 IGBT
259(1)
7.2.2.1 Model Formulation
259(4)
7.2.2.2 Hardware Module Architecture
263(2)
7.2.2.3 Multiple Parallel Devices
265(2)
7.2.3 Electro-Thermal Network
267(1)
7.2.4 Hardware Emulation Results
268(2)
7.3 Physics-Based Nonlinear IGBT/Diode Model
270(22)
7.3.1 Physics-Based Nonlinear p-i-n Diode Model
271(1)
7.3.1.1 Model Formulation
271(1)
7.3.1.2 Model Discretization and Linearization
272(2)
7.3.1.3 Hardware Emulation on FPGA
274(2)
7.3.2 Physics-Based Nonlinear IGBT Model
276(1)
7.3.2.1 Model Formulation
276(3)
7.3.2.2 Model Discretization and Linearization
279(2)
7.3.2.3 Hardware Emulation on FPGA
281(4)
7.3.3 Hardware Emulation Results
285(1)
7.3.3.1 Test circuit
285(1)
7.3.3.2 Results and comparison
286(6)
7.4 IGBT/Diode Curve-Fitting Model
292(8)
7.4.1 Linear Static Curve-fitting Model
293(1)
7.4.1.1 Static Characteristics
293(1)
7.4.1.2 Switching Transients
293(3)
7.4.2 Nonlinear Dynamic Curve-fitting Model
296(2)
7.4.3 Hardware Emulation Results
298(2)
7.5 Summary
300(1)
8 AC-DC Converters
301(76)
8.1 Overview
301(2)
8.2 Detailed Model
303(2)
8.2.1 Detailed Equivalent Circuit Model
304(1)
8.3 Equivalenced Device-Level Model
305(19)
8.3.1 Power Loss Calculation
307(2)
8.3.2 Thermal Network Calculation
309(2)
8.3.3 Hardware Emulation of SM Model on FPGA
311(3)
8.3.4 MMC System Hardware Emulation
314(2)
8.3.5 Real-Time Emulation Results
316(1)
8.3.5.1 Test Circuit and Hardware Resource Utilization
316(2)
8.3.5.2 Results and Comparison for Single-Phase Five-Level MMC
318(6)
8.3.5.3 Results for Three-Phase Nine-Level MMC
324(1)
8.4 Virtual-Line-Partitioned Device-Level Models
324(20)
8.4.1 TLM-Link Partitioning
326(2)
8.4.2 Hardware Design on FPGA
328(1)
8.4.2.1 Hardware Platform
329(1)
8.4.2.2 Controller Emulation
329(1)
8.4.2.3 MMC Emulation on FPGA
330(5)
8.4.3 Real-Time Emulation Results
335(1)
8.4.3.1 MMC
335(7)
8.4.3.2 Induction Machine Driven by Five-Level MMC
342(2)
8.5 MMC Partitioned by Coupled Voltage-Current Sources
344(11)
8.5.1 V-I Coupling
344(2)
8.5.2 Hardware Emulation Case of NBM-Based MMC
346(1)
8.5.2.1 Power Converter HIL Emulation
346(1)
8.5.2.2 HIL Emulation Results and Validation
347(1)
8.5.2.3 Islanded MMC Performance
348(7)
8.5.2.4 MMC-MVDC Performance
355(1)
8.6 Clamped Double Submodule MMC
355(19)
8.6.1 Operation Principles of CDSM
357(2)
8.6.2 Device-Level Modeling Scheme
359(1)
8.6.2.1 Temperature-Dependent Electrical Interface Parameter Calculation
359(2)
8.6.2.2 Device-Level Linearized Transient Waveform Calculation
361(1)
8.6.3 SM-Level Modeling Scheme
362(1)
8.6.4 Converter-Level Modeling Scheme
362(1)
8.6.5 Case Study and Hardware Implementation
363(2)
8.6.5.1 Design Partition
365(2)
8.6.5.2 Latency and Resource Consumption
367(1)
8.6.6 Real-Time Emulation Results and Analysis
368(1)
8.6.6.1 Steady-State Results
368(1)
8.6.6.2 DC Power Flow Control
368(3)
8.6.6.3 DC Fault Transient Results
371(3)
8.7 Summary
374(3)
9 DC-DC Converters
377(20)
9.1 Overview
377(2)
9.2 Buck-Boost Converter
379(2)
9.2.1 System-Level Modeling
379(1)
9.2.2 Hardware Implementation
380(1)
9.3 Solid-State Transformer Modeling
381(13)
9.3.1 MMC Arm Models
382(1)
9.3.1.1 TLM-Stub Model (TLM-S)
382(1)
9.3.1.2 Nonlinear Switch-Based Model (NSM)
383(1)
9.3.1.3 Hybrid Arm Model
384(1)
9.3.2 Three-Phase Saturable Transformer Model
385(1)
9.3.3 SST EMT Model
385(1)
9.3.4 SST HIL Emulation
386(4)
9.3.5 SST Real-Time HIL Emulation Results
390(1)
9.3.5.1 Device-Level Behavior
390(1)
9.3.5.2 Converter Performance
391(1)
9.3.5.3 System Tests
392(2)
9.4 Summary
394(3)
10 DC Circuit Breakers
397(50)
10.1 Overview
397(2)
10.2 HHB in MTDC System
399(3)
10.2.1 MTDC Test System Schematic
399(2)
10.2.2 DC Line Protection
401(1)
10.2.2.1 Voltage Derivative Protection
401(1)
10.2.2.2 Over Current Protection
401(1)
10.3 Proactive Hybrid HVDC Breaker
402(24)
10.3.1 HHB EMT Model
403(1)
10.3.2 Varistor Model
404(2)
10.3.3 General HHB Unit Model
406(1)
10.3.4 Two-Node IGBT Models
407(2)
10.3.5 IGBT Low-Order Nonlinear Behavioral Model
409(1)
10.3.5.1 IGBT Fourth-Order Behavioral Model
409(1)
10.3.5.2 Parameters Extraction
409(1)
10.3.5.3 Sensitivity Analysis
410(1)
10.3.5.4 Model Parallelization
411(1)
10.3.6 Electro-Thermal Network
412(1)
10.3.7 HHB Hardware Implementation on FPGA
412(4)
10.3.8 HHB HIL Emulation Results
416(1)
10.3.8.1 Device-Level Performance
416(8)
10.3.8.2 System-Level Performance
424(2)
10.4 Ultrafast Mechatronic Circuit Breaker
426(18)
10.4.1 Nonlinear Device-Level Thyristor Model
426(1)
10.4.1.1 Basic Device Characteristics
426(2)
10.4.1.2 Scalable Cascaded Thyristor Model
428(3)
10.4.2 UFMCB Modeling
431(2)
10.4.3 Relaxed Scalar Newton-Raphson (RSNR)
433(2)
10.4.4 UFMCB Hardware Design
435(3)
10.4.5 UFMCB Real-Time Tests and Validation
438(1)
10.4.5.1 Four-Terminal DC Grid Test Case
438(1)
10.4.5.2 UFMCB Design Evaluation by HIL System
438(4)
10.4.5.3 UFMCB in HVDC Grid
442(2)
10.5 Summary
444(3)
11 Large-Scale AC and DC Networks
447(84)
11.1 Overview
447(2)
11.2 Spatial Decomposition and Parallelism
449(4)
11.2.1 Functional Decomposition for Large-Scale Real-Time Emulation
449(2)
11.2.2 Hardware Module Parallelism
451(2)
11.3 Multi-FPGA Hardware Design for Real-Time EMT Emulation
453(12)
11.3.1 Case I: 3-FPGA Hardware Design
454(3)
11.3.2 Case II: 10-FPGA Hardware Design
457(3)
11.3.3 Performance and Scalability of the Real-Time EMT Emulator
460(5)
11.4 CIGRE DC Grid Hybrid Modeling Methodology
465(14)
11.4.1 Network Topology
467(1)
11.4.2 Control Scheme
467(1)
11.4.3 Hybrid Modeling Methodology
468(1)
11.4.3.1 Device-Level Electrothermal Model
469(1)
11.4.3.2 Equivalent Circuit Model
469(2)
11.4.3.3 Average Value Model
471(1)
11.4.3.4 Transmission Line Model
471(1)
11.4.4 Real-Time MPSoC-FPGA Based DC Grid Emulator
471(1)
11.4.4.1 System Decomposition
471(1)
11.4.4.2 Hardware Resource Allocation and Task Partitioning
472(2)
11.4.4.3 Design and Implementation
474(1)
11.4.5 Real-Time Emulation Results and Validation
475(1)
11.4.5.1 Steady-State Operation
475(2)
11.4.5.2 Power Flow Command Change
477(1)
11.4.5.3 DC Fault
477(2)
11.5 Real-Time Co-Emulation Framework for Cyber-Physical Systems
479(16)
11.5.1 Communication Network Simulation and Co-Simulation
481(3)
11.5.2 Real-Time Co-Emulation Framework
484(1)
11.5.2.1 RTCE Hardware Architecture
484(3)
11.5.3 Hardware Implementation of RTCE
487(1)
11.5.3.1 Multi-Board EMT Emulation
488(1)
11.5.3.2 Communication Protocol and Implementation
489(2)
11.5.4 Real-Time Emulation Results and Verification
491(1)
11.5.4.1 Processing Delay and Hardware Resource Cost
491(1)
11.5.4.2 Case Study 1: Over-Current Fault
492(1)
11.5.4.3 Case Study 2: Communication Link Failure
493(2)
11.6 Faster-Than-Real-Time Hybrid Dynamic-EMT Emulation of AC-DC Grids
495(15)
11.6.1 Flexible Time-Stepping Algorithm for Dynamic Emulation
496(1)
11.6.1.1 Transient Stability Emulation Methodology
496(1)
11.6.1.2 Local Equipment Based Flexible Time-stepping
497(1)
11.6.2 AC-DC Grid Component Modeling
498(1)
11.6.2.1 AC-DC Grid Interface
498(1)
11.6.2.2 AC Grid Modeling
499(2)
11.6.2.3 DC Grid Modeling
501(2)
11.6.3 FTRT Emulation on FPGAs
503(2)
11.6.4 FTRT Emulation Results and Validation
505(1)
11.6.4.1 Three-Phase-to-Ground Fault
506(1)
11.6.4.2 Generator Outage and Sudden Load Change
507(3)
11.7 Summary
510(21)
Bibliography
513(18)
Appendix A Parameters for Case Studies
531(14)
A.1
Chapter 2
531(1)
A.1.1 Case in Section 2.7
531(1)
A.1.2 Cases in Section 2.8
531(1)
A.2
Chapter 3
531(2)
A.2.1 Cases in Section 3.2
531(1)
A.2.1.1 Cases Study I
531(1)
A.2.1.2 Cases Study II
532(1)
A.2.2 Cases in Section 3.3
532(1)
A.2.2.1 Transformer
532(1)
A.2.2.2 System
532(1)
A.2.3 Cases in Section 3.4
532(1)
A.3
Chapter 4
533(5)
A.3.1 UM Case in Section 4.2
533(1)
A.3.2 Cases in Section 4.3
534(1)
A.3.2.1 State-Space Matrices of Rotating Machines
534(4)
A.3.2.2 Parameters of Rotating Machines
538(1)
A.3.3 MEC Case in Section 4.4
538(1)
A.4
Chapter 5
538(1)
A.5
Chapter 6
539(1)
A.5.1 Cases in Section 6.2
539(1)
A.5.2 Cases in Section 6.3
540(1)
A.6
Chapter 7
540(1)
A.7
Chapter 8
541(1)
A.7.1 Equivalenced Device-Level Model in Section 8.3
541(1)
A.7.2 MMC-IM Case in Section 8.4
541(1)
A.7.3 MVDC Case in Section 8.5
541(1)
A.7.4 MTDC Case in Section 8.6
541(1)
A.8
Chapter 9
541(1)
A.9
Chapter 10
542(1)
A.9.1 HHB Case
542(1)
A.9.2 UFMCB Case
542(1)
A.10
Chapter 11
543(2)
A.10.1 CIGRE B4 DC Grid Test System
543(2)
Index 545
Venkata Dinavahi, PhD, PEng, FIEEE, is a Professor in the Department of Electrical and Computer Engineering at the University of Alberta in Edmonton, Alberta, Canada. He received the BEng degree from the Visveswaraya National Institute of Technology (VNIT), Nagpur, India, in 1993, the MTech degree from the Indian Institute of Technology (IIT) Kanpur, India, in 1996, and a PhD in Electrical and Computer Engineering from the University of Toronto, Ontario, Canada, in 2000. He was the founding chair of the IEEE Power & Energy Society (PES) Task Force on Interfacing Techniques for Simulation Tools from 2006-2014. He contributed to several IEEE PES Working Groups and Task Forces notably in the Analytical Methods for Power Systems (AMPS) committee. He is a Fellow of IEEE, a member of CIGRÉ and a Professional Engineer in the Province of Alberta. He was the recipient of the 2018 Outstanding Engineer Award from the IEEE PES/IAS Northern Canada Chapter.

Ning Lin, PhD, is a Postdoctoral Researcher at the University of Alberta. He received the BSc and MSc degrees in Electrical Engineering from Zhejiang University, China, in 2008 and 2011, respectively, and a PhD in Electrical and Computer Engineering from the University of Alberta, Canada, in 2018. From 2011 to 2014, he worked as an engineer on power system automation, flexible AC transmission system (FACTS), and high-voltage direct current (HVDC). His research interests include electromagnetic transient simulation, transient stability analysis, real-time simulation, AC/DC grids, parallel processing, and high-performance computing of power systems and power electronics.
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