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Implementation of Realtime and Highspeed Phase Detector on FPGA |
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1 | (11) |
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Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform |
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12 | (6) |
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Configurable Embedded Core for Controlling Electro-Mechanical Systems |
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18 | (6) |
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Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors |
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24 | (6) |
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Dynamic Partial Reconfigurable FIR Filter Design |
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30 | (6) |
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Event-Driven Simulation Engine for Spiking Neural Networks on a Chip |
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36 | (10) |
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Towards an Optimal Implementation of MLP in FPGA |
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46 | (6) |
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Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture |
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52 | (7) |
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Quality Driven Dynamic Low Power Reconfiguration of Handhelds |
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59 | (6) |
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An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects |
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65 | (10) |
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Highly Paralellized Architecture for Image Motion Estimation |
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75 | (12) |
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Design Exploration of a Video Pre-processor for an FPGA Based SoC |
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87 | (6) |
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QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection |
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93 | (6) |
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Applications of Small-Scale Reconfigurability to Graphics Processors |
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99 | (10) |
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An Embedded Multi-camera System for Simultaneous Localization and Mapping |
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109 | (6) |
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Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor |
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115 | (7) |
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Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip |
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122 | (6) |
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Handel-C Design Enhancement for FPGA-Based DV Decoder |
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128 | (6) |
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Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform |
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134 | (12) |
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A New VLSI Architecture of Lifting-Based DWT |
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146 | (6) |
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Architecture Based on FPGA's for Real-Time Image Processing |
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152 | (6) |
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Real Time Image Processing on a Portable Aid Device for Low Vision Patients |
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158 | (6) |
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General Purpose Real-Time Image Segmentation System |
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164 | (6) |
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Organization and Architecture |
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Implementation of LPM Address Generators on FPGAs |
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170 | (12) |
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Self Reconfiguring EPIC Soft Core Processors |
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182 | (5) |
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Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs |
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187 | (6) |
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Area/Performance Improvement of NoC Architectures |
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193 | (6) |
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Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array |
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199 | (6) |
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A Flexible Multi-port Caching Scheme for Reconfigurable Platforms |
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205 | (12) |
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Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support |
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217 | (13) |
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A Reconfigurable Data Cache for Adaptive Processors |
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230 | (13) |
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The Emergence of Non-von Neumann Processors |
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243 | (12) |
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Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server |
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255 | (7) |
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A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs |
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262 | (6) |
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A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI |
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268 | (6) |
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PISC: Polymorphic Instruction Set Computers |
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274 | (13) |
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Networks and Communication |
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Generic Network Interfaces for Plug and Play NoC Based Architecture |
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287 | (12) |
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Providing QoS Guarantees in a NoC by Virtual Channel Reservation |
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299 | (12) |
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Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA |
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311 | (6) |
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A Reconfigurable Architecture for MIMO Square Root Decoder |
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317 | (6) |
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Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking |
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323 | (12) |
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Updates on the Security of FPGAs Against Power Analysis Attacks |
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335 | (12) |
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Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems |
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347 | (11) |
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FPGA Implementation of a GF(2m) Tate Pairing Architecture |
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358 | (12) |
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Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA |
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370 | (13) |
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Guerric Meurice de Dormale |
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Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider |
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383 | (6) |
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UNITE: Uniform Hardware-Based Network Intrusion deTection Engine |
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389 | (12) |
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Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs |
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401 | (12) |
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Automatic Compilation Framework for Bloom Filter Based Intrusion Detection |
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413 | (6) |
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A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware |
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419 | (6) |
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Hardware and a Tool Chain for ADRES |
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425 | (6) |
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Integrating Custom Instruction Specifications into C Development Processes |
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431 | (12) |
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A Compiler-Oriented Architecture Description for Reconfigurable Systems |
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443 | (6) |
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Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility |
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449 | (6) |
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High-Level Synthesis Using SPARK and Systolic Array |
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455 | (6) |
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Super Semi-systolic Array-Based Application-Specific PLD Architecture |
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461 | (6) |
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Author Index |
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467 | |