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E-raamat: Reconfigurable Computing: Architectures and Applications: Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 Revised Selected Papers

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  • Sari: Lecture Notes in Computer Science 3985
  • Ilmumisaeg: 03-Aug-2006
  • Kirjastus: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
  • Keel: eng
  • ISBN-13: 9783540368632
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  • Formaat: PDF+DRM
  • Sari: Lecture Notes in Computer Science 3985
  • Ilmumisaeg: 03-Aug-2006
  • Kirjastus: Springer-Verlag Berlin and Heidelberg GmbH & Co. K
  • Keel: eng
  • ISBN-13: 9783540368632

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1 The International Workshop on Recon gurable Computing (ARC) started in 2005 in Algarve, Portugal. The major motivation was to create an event where on-going research e orts as well as more elaborated, interesting and hi- quality work on applied recon gurable computing could be presented and d- cussed. Over the last couple of years recon gurable computing has become a we- known and established research area producing interesting as well as important results in both general and embedded computing systems. It is also getting more and more interest from industry which is attracted by the (design and development) ?exibility as well as the performance improvements that can be expected from this technology. As recon gurablecomputing has blurred the gap between software and hardware, some even speak of a radical new programming paradigm opening a new realm of unseen applications and opportunities. The logo of the ARC workshop is the Nonius, a measurement instrument used in the Portuguese period of discoveries that was invented by Pedro Nunes, a Portuguesemathematician. As the logo suggests,the main motto of ARC is to help to navigate the world of recon gurable computing. Driven by this motto, we hope ARC contributes to solid advances on recon gurable computing.
Applications
Implementation of Realtime and Highspeed Phase Detector on FPGA
1(11)
Andre Guntoro
Peter Zipf
Oliver Soffke
Harald Klingbeil
Martin Kumm
Manfred Glesner
Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform
12(6)
Gerd Van den Branden
Geert Braeckman
Abdellah Touhafi
Erik Dirkx
Configurable Embedded Core for Controlling Electro-Mechanical Systems
18(6)
Rodrigo Piedade
Leonel Sousa
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors
24(6)
J. Gonzalez-Gomez
I. Gonzalez
F. Gomez-Arribas
E. Boemo
Dynamic Partial Reconfigurable FIR Filter Design
30(6)
Yeong-Jae Oh
Hanho Lee
Chong-Ho Lee
Event-Driven Simulation Engine for Spiking Neural Networks on a Chip
36(10)
Rodrigo Agis
Javier Diaz
Eduardo Ros
Richard Carrillo
Eva. M. Ortigosa
Towards an Optimal Implementation of MLP in FPGA
46(6)
E.M. Ortigosa
A. Canas
R. Rodriguez
J. Diaz
S. Mota
Power
Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture
52(7)
Kris Heyrman
Antonis Papanikolaou
Francky Catthoor
Peter Veelaert
Koen Debosschere
Wilfried Philips
Quality Driven Dynamic Low Power Reconfiguration of Handhelds
59(6)
Hiren Joshi
S.S. Verma
G.K. Sharma
An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects
65(10)
Joong-ho Park
Bang-Hyun Sung
Seok-Yoon Kim
Image Processing
Highly Paralellized Architecture for Image Motion Estimation
75(12)
Javier Diaz
Eduardo Ros
Sonia Mota
Rafael Rodriguez-Gomez
Design Exploration of a Video Pre-processor for an FPGA Based SoC
87(6)
Niklas Lepisto
Benny Thornberg
Mattias O'Nils
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
93(6)
Sunil Shukla
Neil W. Bergmann
Jurgen Becker
Applications of Small-Scale Reconfigurability to Graphics Processors
99(10)
Kevin Dale
Jeremy W. Sheaffer
Vinu Vijay Kumar
David P. Luebke
Greg Humphreys
Kevin Skadron
An Embedded Multi-camera System for Simultaneous Localization and Mapping
109(6)
Vanderlei Bonato
Jose A. de Holanda
Eduardo Marques
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor
115(7)
Vu Manh Tuan
Yohei Hasegawa
Naohiro Katsura
Hideharu Amano
Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip
122(6)
Francisco Fons
Mariano Fons
Enrique Canto
Mariano Lopez
Handel-C Design Enhancement for FPGA-Based DV Decoder
128(6)
Slawomir Cichon
Marek Gorgon
Miroslaw Pac
Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform
134(12)
Alex Ngouanga
Gilles Sassatelli
Lionel Torres
Thierry Gil
Andre Borin Suarez
Altamiro Amadeu Susin
A New VLSI Architecture of Lifting-Based DWT
146(6)
Young-Ho Seo
Dong-Wook Kim
Architecture Based on FPGA's for Real-Time Image Processing
152(6)
Ignacio Bravo
Pedro Jimenez
Manuel Mazo
Jose Luis Lazaro
Ernesto Martin
Real Time Image Processing on a Portable Aid Device for Low Vision Patients
158(6)
E. Ros
J. Diaz
S. Mota
F. Vargas-Martin
M.D. Pelaez-Coca
General Purpose Real-Time Image Segmentation System
164(6)
S. Mota
E. Ros
J. Diaz
F. de Toro
Organization and Architecture
Implementation of LPM Address Generators on FPGAs
170(12)
Hui Qin
Tsutomu Sasao
Jon T. Butler
Self Reconfiguring EPIC Soft Core Processors
182(5)
Rainer Scholz
Klaus Buchenrieder
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs
187(6)
S. Roman
J. Septien
H. Mecha
D. Mozos
Area/Performance Improvement of NoC Architectures
193(6)
Mario P. Vestias
Horacio C. Neto
Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array
199(6)
Kwangsup So
Jinsang Kim
Won-Kyung Cho
Young-Soo Kim
Doug Young Suh
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
205(12)
Su-Shin Ang
George Constantinides
Peter Cheung
Wayne Luk
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support
217(13)
Nikolaos Vassiliadis
George Theodoridis
Spiridon Nikolaidis
A Reconfigurable Data Cache for Adaptive Processors
230(13)
D. Benitez
J.C. Moure
D.I. Rexachs
E. Luque
The Emergence of Non-von Neumann Processors
243(12)
Daniel S. Poznanovic
Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server
255(7)
Marcelo Gotz
Florian Dittmann
A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs
262(6)
Manuel G. Gericota
Gustavo R. Alves
Luis F. Lemos
Jose M. Ferreira
A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
268(6)
Minoru Watanabe
Fuminori Kobayashi
PISC: Polymorphic Instruction Set Computers
274(13)
Stamatis Vassiliadis
Georgi Kuzmanov
Stephan Wong
Elena Moscu-Panainte
Georgi Gaydadjiev
Koen Bertels
Dmitry Cheresiz
Networks and Communication
Generic Network Interfaces for Plug and Play NoC Based Architecture
287(12)
Sanjay Pratap Singh
Shilpa Bhoj
Dheera Balasubramanian
Tanvi Nagda
Dinesh Bhatia
Poras Balsara
Providing QoS Guarantees in a NoC by Virtual Channel Reservation
299(12)
Nikolay Kavaldjiev
Gerard J.M. Smit
Pascal T. Wolkotte
Pierre G. Jansen
Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA
311(6)
Milan Tichy
Jan Schier
David Gregg
A Reconfigurable Architecture for MIMO Square Root Decoder
317(6)
Hongzhi Wang
Pierre Leray
Jacques Palicot
Security
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking
323(12)
Nele Mentens
Lejla Batina
Bart Preneel
Ingrid Verbauwhede
Updates on the Security of FPGAs Against Power Analysis Attacks
335(12)
F.-X. Standaert
F. Mace
E. Peeters
J.-J. Quisquater
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems
347(11)
K. Sakiyama
N. Mentens
L. Batina
B. Preneel
I. Verbauwhede
FPGA Implementation of a GF(2m) Tate Pairing Architecture
358(12)
Maurice Keller
Tim Kerins
Francis Crowe
William Marnane
Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA
370(13)
Guerric Meurice de Dormale
Jean-Jacques Quisquater
Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider
383(6)
David Rodriguez
Juan M. Sanchez
Arturo Duran
UNITE: Uniform Hardware-Based Network Intrusion deTection Engine
389(12)
S. Yusuf
W. Luk
M.K.N. Szeto
W. Osborne
Tools
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs
401(12)
Betul Buyukkurt
Zhi Guo
Walid A. Najjar
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection
413(6)
Dinesh C. Suresh
Zhi Guo
Betul Buyukkurt
Walid A. Najjar
A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware
419(6)
Jie Guo
Gleb Belov
Gerhard P. Fettweis
Hardware and a Tool Chain for ADRES
425(6)
Bjorn De Sutter
Bingfeng Mei
Andrei Bartic
Tom Vander Aa
Mladen Berekovic
Jean-Yves Mignolet
Kris Croes
Paul Coene
Miro Cupac
Aissa Couvreur
Andy Folens
Steven Dupont
Bert Van Thielen
Andreas Kanstein
Hong-Seok Kim
Suk Jin Kim
Integrating Custom Instruction Specifications into C Development Processes
431(12)
Jack Whitham
Neil Audsley
A Compiler-Oriented Architecture Description for Reconfigurable Systems
443(6)
Jens Braunes
Rainer G. Spallek
Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility
449(6)
Antonio Carlos S. Beck
Victor F. Gomes
Luigi Carro
High-Level Synthesis Using SPARK and Systolic Array
455(6)
Jae-Jin Lee
Gi-Yong Song
Super Semi-systolic Array-Based Application-Specific PLD Architecture
461(6)
Jae-Jin Lee
Gi-Yong Song
Author Index 467