E-raamat: Reconfigurable Computing: Architectures, Tools and Applications: Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings

Architectures [ Regular Papers].- Architectural Exploration of the ADRES
Coarse-Grained Reconfigurable Array.- A Configurable Multi-ported Register
File Architecture for Soft Processor Cores.- MT-ADRES: Multithreading on
Coarse-Grained Reconfigurable Architecture.- Asynchronous ARM Processor
Employing an Adaptive Pipeline Architecture.- Partially Reconfigurable
Point-to-Point Interconnects in Virtex-II Pro FPGAs.- Systematic
Customization of On-Chip Crossbar Interconnects.- Authentication of FPGA
Bitstreams: Why and How.- Architectures [ Short Papers].- Design of a
Reversible PLD Architecture.- Designing Heterogeneous FPGAs with Multiple
SBs.- Mapping Techniques and Tools [ Regular Papers].- Partial Data Reuse for
Windowing Computations: Performance Modeling for FPGA Implementations.-
Optimized Generation of Memory Structure in Compiling Window Operations onto
Reconfigurable Hardware.- Adapting and Automating XILINXs Partial
Reconfiguration Flow for Multiple Module Implementations.- A Linear
Complexity Algorithm for the Automatic Generation of Convex Multiple Input
Multiple Output Instructions.- Evaluating Variable-Grain Logic Cells Using
Heterogeneous Technology Mapping.- The Implementation of a Coarse-Grained
Reconfigurable Architecture with Loop Self-pipelining.- Hardware/Software
Codesign for Embedded Implementation of Neural Networks.- Synthesis of
Regular Expressions Targeting FPGAs: Current Status and Open Issues.- Mapping
Techniques and Tools [ Short Papers].- About the Importance of Operation
Grouping Procedures for Multiple Word-Length Architecture Optimizations.-
Arithmetic [ Regular Papers].- Switching Activity Models for Power Estimation
in FPGA Multipliers.- Multiplication over on FPGA: A Survey.- A Parallel
Version of the Itoh-Tsujii MultiplicativeInversion Algorithm.- A Fast Finite
Field Multiplier.- Applications [ Regular Papers].- Combining Flash Memory and
FPGAs to Efficiently Implement a Massively Parallel Algorithm for
Content-Based Image Retrieval.- Image Processing Architecture for Local
Features Computation.- A Compact Shader for FPGA-Based Volume Rendering
Accelerators.- Ubiquitous Evolvable Hardware System for Heart Disease
Diagnosis Applications.- FPGA-Accelerated Molecular Dynamics Simulations: An
Overview.- Reconfigurable Hardware Acceleration of Canonical Graph
Labelling.- Reconfigurable Computing for Accelerating Protein Folding
Simulations.- Reconfigurable Parallel Architecture for Genetic Algorithms:
Application to the Synthesis of Digital Circuits.- Applications [ Short
Papers].- A Space Variant Mapping Architecture for Reliable Car
Segmentation.- A Hardware SAT Solver Using Non-chronological Backtracking and
Clause Recording Without Overheads.- Searching the Web with an FPGA Based
Search Engine.- An Acceleration Method for Evolutionary Systems Based on
Iterated Prisoners Dilemma.- Real Time Architectures for Moving-Objects
Tracking.- Reconfigurable Hardware Evolution Platform for a Spiking Neural
Network Robotics Controller.- Multiple Sequence Alignment Using
Reconfigurable Computing.- Simulation of the Dynamic Behavior of
One-Dimensional Cellular Automata Using Reconfigurable Computing.