Muutke küpsiste eelistusi

E-raamat: Robust SRAM Designs and Analysis

5.00/5 (5 hinnangut Goodreads-ist)
, ,
  • Formaat: PDF+DRM
  • Ilmumisaeg: 01-Aug-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461408185
Teised raamatud teemal:
  • Formaat - PDF+DRM
  • Hind: 110,53 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
Robust SRAM Designs and AnalysisSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 01-Aug-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461408185
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

This guide to Static Random Access Memory (SRAM) bitcell design and analysis meets the nano-regime challenges for CMOS devices and such emerging devices as Tunnel FETs. Offers popular SRAM bitcell topologies that mitigate variability, plus exhaustive analysis.
1 Introduction to SRAM
1(30)
1.1 CMOS Technology Scaling
1(1)
1.2 Why SRAM?
2(3)
1.3 SRAM Architecture
5(8)
1.3.1 SRAM Bitcell
6(1)
1.3.2 Address Decoders
7(1)
1.3.3 Precharge Circuit
8(1)
1.3.4 Sense Amplifiers
9(2)
1.3.5 Write Drivers
11(2)
1.4 SRAM Design Issues and Challenges
13(7)
1.4.1 Conflicting Device Size Requirements
14(2)
1.4.2 Process Variation
16(1)
1.4.3 Bitline Leakage Current
16(1)
1.4.4 Partial Write Disturbance
17(2)
1.4.5 Soft Errors
19(1)
1.5 SRAM Bitcell Topologies
20(9)
1.5.1 Non-isolated Read-Port SRAM Bitcell Topologies
21(3)
1.5.2 Isolated Read-Port SRAM Bitcell Topologies
24(3)
1.5.3 Low-Leakage Asymmetric SRAM Bitcell
27(2)
1.6 Summary
29(2)
2 Design Metrics of SRAM Bitcell
31(26)
2.1 Standard 6T SRAM Bitcell: An Overview
31(8)
2.1.1 Read Operation
31(2)
2.1.2 Read SNM Measurement
33(3)
2.1.3 Write Operation
36(1)
2.1.4 Write SNM Measurement
37(1)
2.1.5 Relationships Between Transistor Drive Strengths
38(1)
2.2 Other SRAM Bitcell Stability Metrics
39(6)
2.2.1 N-Curve Stability Metrics
39(3)
2.2.2 Static Voltage and Current Metrics
42(1)
2.2.3 Power Metrics
43(1)
2.2.4 Dependencies of SPNM and WTP
43(1)
2.2.5 Dependence on the Bitcell Ratio
44(1)
2.2.6 Dependence on the Supply Voltage VDD
45(1)
2.3 Bitline Measurement Design Metrics
45(6)
2.3.1 Read Stability Measurement
46(3)
2.3.2 Writeability Measurement
49(2)
2.4 Dynamic Stability Analysis
51(5)
2.4.1 Dynamic Read Stability
52(2)
2.4.2 Dynamic Write Stability
54(2)
2.5 Summary
56(1)
3 Single-Ended SRAM Bitcell Design
57(26)
3.1 Introduction
57(2)
3.2 SRAM Bitcell Topologies
59(3)
3.2.1 Transmission Gate Based Access 6T (TG-6T) SRAM Bitcell
59(2)
3.2.2 Separate Read-Port 8T SRAM Bitcell
61(1)
3.3 Single-Ended 6T SRAM (SE-SRAM) Bitcell
62(5)
3.3.1 Array Organization of SE 6T SRAM Bitcell
64(1)
3.3.2 Read Operation
65(1)
3.3.3 Write Operation
66(1)
3.4 Read Stability and Write Ability Margins
67(4)
3.4.1 Read Stability Margin (SNM)
67(1)
3.4.2 Write-Ability Margin (WAM)
68(3)
3.5 Sizing of Read and Write Assist Transistors in SE 6T Bitcell
71(7)
3.5.1 Sizing of Read Assist Transistor
72(4)
3.5.2 Sizing of Write Assist Transistor
76(1)
3.5.3 Floor Plan to Eliminate the PWD
76(2)
3.6 Performance and Power Dissipation
78(4)
3.6.1 Read Access Time Distribution
79(1)
3.6.2 Power and Leakage Dissipation
80(2)
3.7 Summary
82(1)
4 2-Port SRAM Bitcell Design
83(30)
4.1 Introduction
83(2)
4.2 Existing 2-Port SRAM Bitcells
85(3)
4.2.1 Standard 8T SRAM Bitcell
85(1)
4.2.2 Differential Biasing 7T SRAM Bitcell
86(2)
4.3 2-Port 6T SRAM Bitcell
88(3)
4.3.1 Array Organization
89(1)
4.3.2 Read and Write Operations in 2-Port 6T Bitcell
90(1)
4.4 Reconfigured Read-Port of a 2-Port 6T Bitcell
91(8)
4.4.1 RBL Leakage and Gate Tunnelling Currents
94(1)
4.4.2 Read Bitline Leakage Scenario-1
95(1)
4.4.3 Read Bitline Leakage Scenario-2
96(3)
4.5 Simultaneous Read/Write Access in 2-Port 6T-SRAM
99(2)
4.5.1 Reading Word A
100(1)
4.5.2 Writing Word A
100(1)
4.5.3 Simultaneous R/W Word A and C
101(1)
4.6 SRAM Process Variation Sensitivity
101(4)
4.7 Area, Power and Performance of the 2-Port SRAM Bitcells
105(6)
4.7.1 Area Overhead with Multi-port Capabilities
106(3)
4.7.2 Power Dissipation
109(1)
4.7.3 Performance
109(2)
4.8 Summary
111(2)
5 SRAM Bitcell Design Using Unidirectional Devices
113(24)
5.1 Introduction
113(2)
5.2 Tunneling Transistors
115(3)
5.3 Development of TFETs Behavioural Model
118(2)
5.4 Implications of Asymmetric Current on SRAM Design
120(7)
5.4.1 Inward Access Transistors SRAM Bitcell Topology
122(3)
5.4.2 Outward Access Transistors SRAM Bitcell Topology
125(2)
5.5 A Case Study of a 6T TFET SRAM Bitcell Design
127(3)
5.5.1 Read Operation in 6T TFET SRAM Bitcell
128(1)
5.5.2 Write Operation in 6T TFET SRAM Bitcell
129(1)
5.6 SRAM Bitcell Design Metrics
130(5)
5.6.1 SRAM Bitcell Stability
131(1)
5.6.2 SRAM Bitcell Performance
132(2)
5.6.3 Leakage Power
134(1)
5.6.4 Area
134(1)
5.7 Summary
135(2)
6 NBTI and Its Effect on SRAM
137(20)
6.1 Introduction
137(2)
6.2 The Physics of Negative Bias Temperature Instability (NBTI) and Its Impact
139(3)
6.3 NBTI Model
142(1)
6.4 SRAM Bitcells Under NBTI
143(3)
6.5 Leakage Energy Saving Techniques in Caches
146(3)
6.5.1 Leakage Energy Saving Cache Configurations
147(2)
6.6 Stability Recovery Under Different Cache Configurations
149(3)
6.6.1 Read SNM Recovery
149(2)
6.6.2 WNM Recovery
151(1)
6.7 Effect of NBTI Under Process Variation
152(3)
6.7.1 Read SNM Distribution Under Process Variation
153(1)
6.7.2 Leakage Current Distribution Under Process Variations
154(1)
6.8 Summary
155(2)
References 157(8)
Index 165
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97814614081852e.html
Märksõnad: