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E-raamat: Semiconductors: Integrated Circuit Design for Manufacturability

(Cypress Semiconductor, San Diego, CA, USA)
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Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. Thats why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details.

Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotlight on detailed engineering enhancements and their implications for device functionality, in contrast, this one offers, among other things, crucial, valuable historical background and roadmapping, all illustrated with examples.

Presents actual test cases that illustrate product challenges, examine possible solution strategies, and demonstrate how to select and implement the right one

This book shows that DfM is a powerful generic engineering concept with potential extending beyond its usual application in automated layout enhancements centered on proximity correction and pattern density. This material explores the concept of ICD for production by breaking down its major steps: product definition, design, layout, and manufacturing. Averting extended discussion of technology, techniques, or specific device dimensions, the author also avoids the clumsy chapter architecture that can hinder other books on this subject. The result is an extremely functional, systematic presentation that simplifies existing approaches to DfM, outlining a clear set of criteria to help readers assess reliability, functionality, and yield. With careful consideration of the economic and technical trade-offs involved in ICD for manufacturing, this reference addresses techniques for physical, electrical, and logical design, keeping coverage fresh and concise for the designers, manufacturers, and researchers defining product architecture and research programs.
Preface xi
Acknowledgments xiii
About the Author xv
1 Introduction 1(22)
1.1 Design for Manufacturability: Integrated Circuit Manufacturing versus Industry Legacy
1(3)
1.2 Why Should One Read This Book?
4(1)
1.3 The 2D Paradigm, Rules, and Optimization
5(2)
1.4 Three DfM Product Questions
7(3)
1.5 Smart Goals
10(3)
1.5.1 Significant
10(1)
1.5.2 Measurable
10(1)
1.5.2.1 Manufacturing Yield
10(1)
1.5.3 Attainable
11(1)
1.5.4 Relevant
11(1)
1.5.5 Timely
12(11)
1.5.5.1 Verification Methodology
12(1)
1.6 DfM: Is/Is Not
13(3)
1.7 This Book: Is/Is Not
16(5)
References
21(2)
2 Migrating Industrial DfM into IC Manufacturing 23(68)
2.1 Introduction: Universal Design for Manufacturability Principles
23(10)
2.1.1 The Rule of 10
27(3)
2.1.2 Concurrent Engineering and Standardization: Design, Process, Product
30(3)
2.2 Design-for-Reliability: Reliability First
33(33)
2.2.1 Definitions
33(4)
2.2.2 Material-Dependent IC Reliability
37(29)
2.2.2.1 Metals
38(6)
2.2.2.2 Dielectrics
44(13)
2.2.2.3 Semiconductors
57(9)
2.3 Design for Test
66(6)
2.3.1 DfT Techniques
68(3)
2.3.2 Power-Aware DfT
71(1)
2.4 Yield
72(13)
2.4.1 Parametric Yield
77(1)
2.4.2 Functional, Sort, and Class Yield
78(7)
2.5 Summary
85(1)
References
86(5)
3 IC DfM for Devices and Products 91(68)
3.1 Introduction
91(1)
3.2 DfM for MOSFETs and Standard Cells
92(11)
3.2.1 Device Models and Design Intent
96(9)
3.2.1.1 Static Random Access Memory Cells
96(6)
3.2.1.2 Stitch Cells
102(1)
3.3 DfM at Block and Die Levels: Rules and Best Practices
103(2)
3.4 1D, 2D, 3D, 4D Variability Compromises
105(47)
3.4.1 1D: Line/Space Pitch
107(1)
3.4.2 2D: Pattern Enhancement Techniques
108(26)
3.4.2.1 OPC
110(7)
3.4.2.2 Electrical Impact
117(7)
3.4.2.3 Inverse Lithography
124(2)
3.4.2.4 Mask Manufacturability
126(8)
3.4.3 3D: On and Off Die
134(16)
3.4.3.1 Planarization
134(10)
3.4.3.2 Etch Selectivity Control
144(3)
3.4.3.3 Off-Die Architectures
147(3)
3.4.4 4D: Time and Voltage Domains
150(2)
3.5 Summary: DfM vs. Process Variability
152(3)
References
155(4)
4 Fab Implementation: MfD Response 159(32)
4.1 Introduction
159(5)
4.2 Lithography
164(18)
4.2.1 MfD Cost of Pattern Resolution
165(13)
4.2.1.1 Extreme Ultraviolet Lithography
166(3)
4.2.1.2 Nanoimprint Lithography
169(4)
4.2.1.3 Double-Patterning Techniques
173(5)
4.2.2 Overlay Road Mapping
178(4)
4.3 Planarization
182(5)
4.4 Summary
187(1)
References
188(3)
5 DfM Metrics 191(26)
5.1 Introduction
191(1)
5.2 Layout Quality
192(5)
5.2.1 Variability
192(1)
5.2.2 Feedback Loop
193(1)
5.2.3 Critical Area
193(2)
5.2.4 OPC Friendliness
195(1)
5.2.5 Other DfM Metrics
195(2)
5.3 Mask Ratio
197(7)
5.3.1 Definition
198(1)
5.3.2 Execution
199(1)
5.3.3 Verification: Model Accuracy and Hot Spots
200(1)
5.3.4 Correlation to Fab Yield
201(3)
5.4 FMEA and RoI
204(10)
5.4.1 DRC/DfM Prioritization
207(1)
5.4.2 Time to RoI
207(4)
5.4.3 FMEA-RoI Correlation
211(3)
5.5 Summary
214(1)
References
215(2)
6 Summary and Work Ahead 217(2)
Index 219
Artur Balasinski is a Technology Design Integration Manager for Cypress Semiconductor in San Jose, California. He received the Ph.D.E.E. degree in MOS technology from Warsaw University of Technology, Poland, where he continued as assistant professor. He then joined research team at Yale University, New Haven, CT, to continue studies on rad-hard devices. Subsequently, he joined the IC industry, first the R&D at STMicroelectronics, working on CMOS process transfers, and since 1997, at Cypress Semiconductor where, as Principal Technology-Design Integration (TDI) engineer, he developed expertise in characterization, process integration, optical proximity correction, and design rules. He has authored or coauthored about 90 papers (3 of them received Best Paper Awards), a book chapter, and has 15 U.S. patents. A member of BACUS Photomask Steering Committee, over the recent years, he attended SPIE, BACUS, VLSI, IEDM conferences where he formulated his views on DfM, as presented in several invited papers and special sessions.
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