Preface |
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xix | |
Acknowledgements |
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xxv | |
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xxvii | |
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1 Introduction to ΣΔ Modulators: Fundamentals, Basic Architecture and Performance Metrics |
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1 | (28) |
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1.1 Basics of Analog-to-Digital Conversion |
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2 | (7) |
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3 | (1) |
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4 | (1) |
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1.1.3 Quantization White Noise Model |
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5 | (3) |
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8 | (1) |
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1.2 Sigma-Delta Modulation |
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9 | (4) |
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1.2.1 From Noise-shaped Systems to ΣΔ Modulators |
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10 | (1) |
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1.2.2 Performance Metrics of ΣΔMs |
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11 | (2) |
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1.3 The First-order ΣΔ Modulator |
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13 | (3) |
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1.4 Performance Enhancement and Taxonomy of ΣΔMs |
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16 | (3) |
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1.4.1 ΣΔM System-level Design Parameters and Strategies |
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17 | (1) |
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1.4.2 Classification of ΣΔMs |
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18 | (1) |
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1.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs |
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19 | (3) |
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1.5.1 Some Words about ΣΔ Decimators |
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20 | (2) |
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22 | (3) |
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1.6.1 System Design Trade-offs and Signal Processing in ΣΔ DACs |
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22 | (2) |
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1.6.2 Implementation of Digital ΣΔMs used in DACs |
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24 | (1) |
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25 | (4) |
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26 | (3) |
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2 Taxonomy of ΣΔ Architectures |
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29 | (54) |
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2.1 Second-order ΣΔ Modulators |
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30 | (5) |
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2.1.1 Alternative Representations of Second-order ΣΔMs |
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31 | (3) |
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2.1.2 Second-Order ΣΔM with Unity STF |
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34 | (1) |
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2.2 High-order Single-loop ΣΔM |
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35 | (4) |
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2.3 Cascade ΣΔ Modulators |
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39 | (10) |
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2.3.1 SMASH ΣΔM Architectures |
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46 | (3) |
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2.4 Multi-bit ΣΔ Modulators |
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49 | (6) |
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2.4.1 Influence of Multi-bit DAC Errors |
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49 | (1) |
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2.4.2 Dynamic Element Matching Techniques |
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50 | (3) |
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53 | (1) |
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2.4.3.1 Dual-quantization Single-loop ΣΔMs |
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53 | (1) |
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2.4.3.2 Dual-quantization Cascade ΣΔMs |
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54 | (1) |
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2.5 Band-pass ΣΔ Modulators |
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55 | (9) |
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56 | (2) |
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2.5.2 The z → -z2 LP--BP Transformation |
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58 | (1) |
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2.5.3 BP-ΣΔMs with Optimized NTF |
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58 | (3) |
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2.5.4 Time-interleaved and Polyphase BP-ΣΔMs |
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61 | (3) |
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2.6 Continuous-time ZA Modulators: Architecture and Basic Concepts |
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64 | (6) |
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2.6.1 An Intuitive Analysis of CT-ΣΔMs |
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66 | (3) |
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2.6.2 Some Words about Alias Rejection in CT-ΣΔMs |
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69 | (1) |
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2.7 DT--CT Transformation of ΣΔMs |
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70 | (4) |
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2.7.1 The Impulse-invariant Transformation |
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70 | (2) |
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2.7.2 DT--CT Transformation of a Second-order ΣΔM |
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72 | (2) |
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2.8 Direct Synthesis of CT-ΣΔMs |
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74 | (2) |
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76 | (7) |
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76 | (7) |
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3 Circuit Errors in Switched-capacitor ΣΔ Modulators |
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83 | (40) |
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3.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators |
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84 | (2) |
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3.2 Finite Amplifier Gain in SC-ΣΔMs |
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86 | (4) |
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3.3 Capacitor Mismatch in SC-ΣΔMs |
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90 | (1) |
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3.4 Integrator Settling Error in SC-ΣΔMs |
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91 | (10) |
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3.4.1 Behavioral Model for the Integrator Settling |
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91 | (4) |
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3.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product |
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95 | (3) |
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3.4.3 Nonlinear Effect of Finite Amplifier Slew Rate |
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98 | (2) |
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3.4.4 Effect of Finite Switch On-resistance |
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100 | (1) |
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3.5 Circuit Noise in SC-ΣΔ Ms |
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101 | (4) |
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3.6 Clock Jitter in SC-ΣΔMs |
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105 | (2) |
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3.7 Sources of Distortion in SC-ΣΔMs |
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107 | (4) |
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3.7.1 Nonlinear Amplifier Gain |
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107 | (2) |
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3.7.2 Nonlinear Switch On-Resistance |
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109 | (2) |
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3.8 Case Study: High-level Sizing of a ΣΔM |
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111 | (8) |
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3.8.1 Ideal Modulator Performance |
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111 | (1) |
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112 | (3) |
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115 | (1) |
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116 | (1) |
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3.8.5 Overall High-Level Sizing and Noise Budget |
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117 | (2) |
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119 | (4) |
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119 | (4) |
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4 Circuit Errors and Compensation Techniques in Continuous-time EA Modulators |
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123 | (42) |
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4.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators |
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123 | (1) |
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4.2 CT Integrators and Resonators |
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124 | (2) |
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4.3 Finite Amplifier Gain in CT-ΣΔMs |
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126 | (2) |
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4.4 Time-constant Error in CT-ΣΔMs |
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128 | (2) |
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4.5 Finite Integrator Dynamics in CT-ΣΔMs |
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130 | (4) |
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4.5.1 Effect of Finite Gain-Bandwidth Product on CT-ΣΔMs |
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131 | (2) |
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4.5.2 Effect of Finite Slew Rate on CT-ΣΔMs |
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133 | (1) |
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4.6 Sources of Distortion in CT-ΣΔMs |
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134 | (3) |
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4.6.1 Nonlinearities in the Front-end Integrator |
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134 | (2) |
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4.6.2 Intersymbol Interference in the Feedback DAC |
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136 | (1) |
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4.7 Circuit Noise in CT-ΣΔMs |
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137 | (3) |
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4.7.1 Noise Analysis Considering NRZ Feedback DACs |
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137 | (2) |
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4.7.2 Noise Analysis Considering SC Feedback DACs |
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139 | (1) |
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4.8 Clock Jitter in CT-ΣΔMs |
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140 | (9) |
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4.8.1 Jitter in Return-to-zero DACs |
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141 | (1) |
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4.8.2 Jitter in Non-return-to-zero DACs |
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142 | (2) |
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4.8.3 Jitter in Switched-capacitor DACs |
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144 | (1) |
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4.8.4 Lingering Effect of Clock Jitter Error |
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145 | (2) |
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4.8.5 Reducing the Effect of Clock Jitter with FIR and Sine-shaped DACs |
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147 | (2) |
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4.9 Excess Loop Delay in CT-ΣΔMs |
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149 | (6) |
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4.9.1 Intuitive Analysis of ELD |
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149 | (2) |
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4.9.2 Analysis of ELD based on Impulse-invariant DT-CT Transformation |
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151 | (3) |
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4.9.3 Alternative ELD Compensation Techniques |
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154 | (1) |
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4.10 Quantizer Metastability in CT-ΣΔMs |
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155 | (4) |
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159 | (6) |
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160 | (5) |
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5 Behavioral Modeling and High-level Simulation |
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165 | (70) |
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5.1 Systematic Design Methodology of ΣΔ Modulators |
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165 | (4) |
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5.1.1 System Partitioning and Abstraction Levels |
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167 | (1) |
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167 | (2) |
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5.2 Simulation Approaches for the High-level Evaluation of ΣΔMs |
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169 | (4) |
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5.2.1 Alternatives to Transistor-level Simulation |
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169 | (2) |
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5.2.2 Event-driven Behavioral Simulation Technique |
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171 | (1) |
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5.2.3 Programming Languages and Behavioral Modeling Platforms |
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172 | (1) |
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5.3 Implementing ΣΔM Behavioral Models |
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173 | (15) |
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5.3.1 From Circuit Analysis to Computational Algorithms |
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173 | (2) |
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5.3.2 Time-domain versus Frequency-domain Behavioral Models |
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175 | (3) |
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5.3.3 Implementing Time-domain Behavioral Models in MATLAB |
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178 | (4) |
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5.3.4 Building Time-domain Behavioral Models as SIMULINK C-MEX S-functions |
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182 | (6) |
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5.4 Efficient Behavioral Modeling of ZAM Building Blocks using C-MEX S-functions |
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188 | (21) |
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5.4.1 Modeling of SC Integrators using S-functions |
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188 | (2) |
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5.4.1.1 Capacitor Mismatch and Nonlinearity |
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190 | (1) |
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5.4.1.2 Input-referred Thermal Noise |
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191 | (3) |
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5.4.1.3 Switch On-resistance Dynamics |
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194 | (3) |
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5.4.1.4 Incomplete Settling Error |
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197 | (3) |
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5.4.2 Modeling of CT Integrators using S-functions |
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200 | (1) |
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5.4.2.1 Single-pole Gm-C Model |
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200 | (1) |
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5.4.2.2 Two-pole Dynamics Model |
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201 | (2) |
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5.4.2.3 Modeling Transconductors as S-functions |
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203 | (2) |
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5.4.3 Behavioral Modeling of Quantizers using S-functions |
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205 | (1) |
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5.4.3.1 Modeling Multi-level ADCs as S-functions |
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205 | (2) |
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5.4.3.2 Modeling Multi-level DACs as S-functions |
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207 | (2) |
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5.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs |
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209 | (7) |
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5.5.1 Model Libraries Included in SIMSIDES |
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210 | (1) |
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5.5.2 Structure of SIMSIDES and its User Interface |
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211 | (1) |
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5.5.2.1 Creating a New EAM Block Diagram |
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212 | (3) |
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5.5.2.2 Setting Model Parameters |
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215 | (1) |
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5.5.2.3 Simulation Analyses |
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215 | (1) |
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5.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs |
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216 | (15) |
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5.6.1 SC Second-order Single-Bit ΣΔM |
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216 | (2) |
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5.6.1.1 Effect of Amplifier Finite DC Gain |
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218 | (1) |
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5.6.1.2 Effect of Thermal Noise |
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218 | (2) |
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5.6.1.3 Effect of the Incomplete Settling Error |
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220 | (1) |
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5.6.1.4 Cumulative Effect of All Errors |
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221 | (3) |
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5.6.2 CT Fifth-order Cascade 3-2 Multi-bit ΣΔM |
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224 | (3) |
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5.6.2.1 Effect of Nonideal Effects |
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227 | (2) |
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5.6.2.2 High-level Synthesis and Verification |
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229 | (2) |
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231 | (4) |
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231 | (4) |
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6 Automated Design and Optimization of ΣΔMs |
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235 | (36) |
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6.1 Architecture Exploration and Selection: Schreier's Toolbox |
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236 | (9) |
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6.1.1 Basic Functions of Schreier's Delta-Sigma Toolbox |
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236 | (2) |
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6.1.2 Synthesis of a Fourth-order CRFF LP/BP SC-ΣΔM with Tunable Notch |
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238 | (2) |
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6.1.3 Synthesis of a Fourth-order BP CT-ΣΔM with Tunable Notch |
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240 | (5) |
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6.2 Optimization-based High-level Synthesis of ΣΔ Modulators |
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245 | (10) |
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6.2.1 Combining Behavioral Simulation and Optimization |
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246 | (1) |
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6.2.2 Using Simulated Annealing as Optimization Engine |
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247 | (6) |
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6.2.3 Combining SIMSIDES with MATLAB Optimizers |
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253 | (2) |
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6.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs |
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255 | (4) |
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6.3.1 Hardware Emulation of CT-ΣΔMs on an FPGA |
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257 | (1) |
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6.3.2 GPU-accelerated Computing of CT-ΣΔMs |
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258 | (1) |
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6.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs |
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259 | (10) |
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6.4.1 Combining MOEA with SIMSIDES |
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261 | (1) |
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6.4.2 Applying MOEA and SIMSIDES to the Synthesis of CT-ΣΔMs |
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262 | (7) |
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269 | (2) |
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269 | (2) |
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7 Electrical Design of ΣΔMs: From Systems to Circuits |
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271 | (30) |
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272 | (7) |
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7.1.1 SC Integrator Macromodel |
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272 | (1) |
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7.1.1.1 Switch Macromodel |
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272 | (2) |
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274 | (1) |
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7.1.2 CT Integrator Macromodel |
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274 | (1) |
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7.1.2.1 Active-RC Integrators |
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274 | (1) |
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274 | (1) |
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7.1.3 Nonlinear OTA Transconductor |
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275 | (1) |
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7.1.4 Embedded Flash ADC Macromodel |
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276 | (1) |
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7.1.5 Feedback DAC Macromodel |
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277 | (2) |
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7.2 Examples of ΣΔM Macromodels |
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279 | (7) |
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7.2.1 SC Second-order Example |
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279 | (4) |
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7.2.2 Second-order Active-RC ΣΔM |
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283 | (3) |
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7.3 Including Noise in Transient Electrical Simulations of ΣΔMs |
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286 | (8) |
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7.3.1 Generating and Injecting Noise Data Sequences in HSPICE |
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287 | (2) |
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7.3.2 Analyzing the Impact of the Main Noise Sources in SC Integrators |
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289 | (1) |
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7.3.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations |
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289 | (4) |
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7.3.4 Test Bench to Include Noise in the Simulation of ΣΔMs |
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293 | (1) |
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7.4 Processing EAM Output Results of Electrical Simulations |
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294 | (4) |
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298 | (3) |
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298 | (3) |
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8 Design Considerations of ZAM Subcircuits |
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301 | (40) |
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8.1 Design Considerations of CMOS Switches |
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302 | (6) |
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8.1.1 Trade-Off Between Ron and the CMOS Switch Drain/Source Parasitic Capacitances |
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302 | (1) |
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8.1.2 Characterizing the Nonlinear Behavior of Ron |
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302 | (2) |
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8.1.3 Influence of Technology Downscaling on the Design of Switches |
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304 | (1) |
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8.1.4 Evaluating Harmonic Distortion due to CMOS Switches |
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305 | (3) |
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8.2 Design Considerations of Operational Amplifiers |
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308 | (9) |
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8.2.1 Typical Amplifier Topologies |
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309 | (2) |
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8.2.2 Common-mode Feedback Networks |
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311 | (2) |
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8.2.3 Characterization of the Amplifier in AC |
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313 | (1) |
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8.2.4 Characterization of the Amplifier in DC |
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313 | (3) |
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8.2.5 Characterization of the Amplifier Gain Nonlinearity |
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316 | (1) |
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8.3 Design Considerations of Transconductors |
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317 | (7) |
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8.3.1 Highly Linear Front-end Transconductor |
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318 | (2) |
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8.3.2 Loop-filter Transconductors |
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320 | (3) |
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8.3.3 Widely Programmable Transconductors |
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323 | (1) |
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8.4 Design Considerations of Comparators |
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324 | (8) |
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8.4.1 Regenerative Latch-based Comparators |
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325 | (2) |
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8.4.2 Design Guidelines of Comparators |
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327 | (1) |
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8.4.3 Characterization of Offset and Hysteresis Based on the Input-ramp Method |
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328 | (1) |
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8.4.4 Characterization of Offset and Hysteresis Based on the Bisectional Method |
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328 | (2) |
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8.4.5 Characterizing the Comparison Time |
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330 | (2) |
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8.5 Design Considerations of Current-Steering DACs |
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332 | (6) |
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8.5.1 Fundamentals and Basic Concepts of CS DACs |
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333 | (1) |
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8.5.2 Practical Realization of CS DACs |
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333 | (3) |
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8.5.3 Current Cell Circuits, Error Limitations, and Design Criteria |
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336 | (1) |
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8.5.4 CS 4-bit DAC Example |
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336 | (2) |
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338 | (3) |
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338 | (3) |
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9 Practical Realization of ΣΔMs: From Circuits to Chips |
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341 | (48) |
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9.1 Auxiliary ΣΔM Building Blocks |
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341 | (7) |
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9.1.1 Clock-phase Generators |
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342 | (1) |
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342 | (1) |
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342 | (2) |
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9.1.1.3 Phase Distribution |
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344 | (1) |
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9.1.2 Generation of Common-mode Voltage, Reference Voltage, and Bias Currents |
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345 | (1) |
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345 | (1) |
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9.1.2.2 Reference Voltage Generator |
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345 | (1) |
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9.1.2.3 Master Bias Current Generator |
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346 | (1) |
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9.1.2.4 Common-mode Voltage Generator |
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346 | (1) |
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9.1.3 Additional Digital Logic |
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347 | (1) |
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9.2 Layout Design, Floorplanning, and Practical Issues |
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348 | (6) |
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9.2.1 Layout Floorplanning |
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348 | (1) |
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9.2.1.1 Divide Layout into Different Parts or Regions |
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348 | (1) |
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9.2.1.2 Shield Sensitive ΣΔM Analog Subcircuits from Switching Noise |
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349 | (1) |
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9.2.1.3 Buses to Distribute Signals Shared by Different EAM Pans |
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349 | (1) |
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9.2.1.4 Be Obsessive about Layout Symmetry and Details of Analog Parts |
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349 | (1) |
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350 | (1) |
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9.2.3 Importance of Layout Verification and Catastrophic Failure |
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350 | (4) |
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9.3 Chip Package, Test PCB, and Experimental Setup |
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354 | (1) |
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9.3.1 Bonding Diagram and Package |
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354 | (1) |
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355 | (1) |
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9.4 Experimental Test Set-Up |
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355 | (4) |
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9.4.1 Planning the Type and Number of Instruments Needed |
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357 | (1) |
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9.4.2 Connecting Lab Instruments |
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357 | (1) |
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9.4.3 Measurement Set-Up Example |
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358 | (1) |
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9.5 EAM Design Examples and Case Studies |
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359 | (26) |
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9.5.1 Programmable-gain ΣΔMs for High Dynamic Range Sensor Interfaces |
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360 | (1) |
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9.5.1.1 Main Design Criteria and Performance Limitations |
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361 | (1) |
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9.5.1.2 SC Realization with Programmable Gain and Double Sampling |
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362 | (1) |
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9.5.1.3 Influence of Chopper Frequency on Flicker Noise |
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362 | (2) |
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9.5.2 Reconfigurable SC-ΣΔMs for Multi-standard Direct Conversion Receivers |
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364 | (3) |
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9.5.2.1 Power-scaling Circuit Techniques |
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367 | (1) |
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9.5.2.2 Experimental Results |
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368 | (1) |
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9.5.3 Using Widely-programmable Gm-LC BP-ΣΔMs for RF Digitizers |
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368 | (3) |
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9.5.3.1 Application Scenario |
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371 | (1) |
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9.5.3.2 Gm-LC BP-ΣΔM High-level Sizing |
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371 | (4) |
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9.5.3.3 BP CT-ΣΔM Loop-Filter Reconfiguration Techniques |
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375 | (3) |
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9.5.3.4 Embedded 4-bit Quantizer with Calibration |
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378 | (4) |
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9.5.3.5 Biasing, Digital Control Programmability and Testability |
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382 | (3) |
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385 | (4) |
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386 | (3) |
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10 Frontiers, Trends and Challenges: Towards Next-generation ΣΔ Modulators |
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389 | (74) |
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10.1 State-of-the-Art ADCs: Nyquist-rate versus ZA Converters |
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390 | (3) |
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391 | (1) |
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392 | (1) |
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10.2 Comparison of Different Categories of ΣΔ ADCs |
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393 | (15) |
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10.2.1 Aperture Plot of ΣΔMs |
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406 | (1) |
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10.2.2 Energy Plot of ΣΔMs |
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407 | (1) |
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10.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs |
|
|
408 | (7) |
|
|
408 | (2) |
|
10.3.2 Technology used in State-of-the-Art ΣΔMs |
|
|
410 | (1) |
|
10.3.3 Single-Loop versus Cascade ΣΔMs |
|
|
410 | (1) |
|
10.3.4 Single-bit versus Multi-bit ΣΔMs |
|
|
411 | (2) |
|
10.3.5 Low-pass versus Band-pass ΣΔMs |
|
|
413 | (2) |
|
10.3.6 Emerging ZAM Techniques |
|
|
415 | (1) |
|
10.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion |
|
|
415 | (3) |
|
10.5 Enhanced Cascade ΣΔMs |
|
|
418 | (5) |
|
|
418 | (1) |
|
10.5.2 Two-stage 0-L MASH |
|
|
419 | (1) |
|
10.5.3 Stage-sharing Cascade ΣΔMs |
|
|
420 | (1) |
|
10.5.4 Multi-rate and Hybrid CT/DT ΣΔMs |
|
|
420 | (1) |
|
10.5.4.1 Upsampling Cascade MR-ΣΔMs |
|
|
421 | (1) |
|
10.5.4.2 Downsampling Hybrid CT/DT Cascade MR-ΣΔMs |
|
|
422 | (1) |
|
10.6 Power-efficient ZAM Loop-filter Techniques |
|
|
423 | (5) |
|
10.6.1 Inverter-based ΣΔMs |
|
|
423 | (1) |
|
10.6.2 Hybrid Active/Passive and Amplifier-less ΣΔMs |
|
|
424 | (2) |
|
10.6.3 Power-efficient Amplifier Techniques |
|
|
426 | (2) |
|
10.7 Hybrid ZAM/Nyquist-rate ADCs |
|
|
428 | (3) |
|
10.7.1 Multi-bit ZAM Quantizers based on Nyquist-rate ADCs |
|
|
428 | (1) |
|
10.7.2 Incremental ZA ADCs |
|
|
429 | (2) |
|
|
431 | (5) |
|
10.8.1 ΣΔMs with VCO/PWM-based Quantization |
|
|
432 | (1) |
|
10.8.2 Scaling-friendly Mostly-digital ΣΔMs |
|
|
433 | (1) |
|
|
434 | (2) |
|
10.9 DAC Techniques for High-performance CT-ΣΔMs |
|
|
436 | (1) |
|
10.10 Classification of State-of-the-Art References |
|
|
437 | (1) |
|
10.11 Summary and Conclusions |
|
|
437 | (26) |
|
|
438 | (25) |
|
A State-space Analysis of Clock Jitter in CT-ΣΔMs |
|
|
463 | (6) |
|
A.1 State-space Representation of NTF (z) |
|
|
463 | (2) |
|
A.2 Expectation Value of (Δqn)2 |
|
|
465 | (1) |
|
A.3 In-band Noise Power due to Clock Jitter |
|
|
466 | (3) |
|
|
467 | (2) |
|
|
469 | (22) |
|
B.1 Getting Started: Installing and Running SIMSIDES |
|
|
470 | (1) |
|
B.2 Building and Editing SAM Architectures in SIMSIDES |
|
|
470 | (3) |
|
B.3 Analyzing ΣΔMs in SIMSIDES |
|
|
473 | (7) |
|
B.3.1 Node Spectrum Analysis |
|
|
474 | (1) |
|
B.3.2 Integrated Power Noise |
|
|
474 | (1) |
|
|
475 | (1) |
|
B.3.4 Harmonic Distortion |
|
|
475 | (2) |
|
B.3.5 Integral and Differential Non-Linearity |
|
|
477 | (1) |
|
B.3.6 Multi-tone Power Ratio |
|
|
477 | (1) |
|
|
478 | (1) |
|
B.3.8 Parametric Analysis |
|
|
478 | (1) |
|
B.3.9 Monte Carlo Analysis |
|
|
479 | (1) |
|
B.4 Optimization Interface |
|
|
480 | (2) |
|
B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs |
|
|
482 | (7) |
|
B 5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES |
|
|
482 | (1) |
|
B.5.2 Setting Model Parameters |
|
|
482 | (2) |
|
B.5.3 Computing the Output Spectrum |
|
|
484 | (2) |
|
B.5.4 SNR versus Input Amplitude Level |
|
|
486 | (1) |
|
B.5.5 Parametric Analysis Considering Only One Parameter |
|
|
487 | (1) |
|
B.5.6 Parametric Analysis Considering Two Parameters |
|
|
488 | (1) |
|
B.5.7 Computing Histograms |
|
|
489 | (1) |
|
|
489 | (2) |
|
C SIMSIDES Block Libraries and Models |
|
|
491 | (32) |
|
C.1 Overview of SIMSIDES Libraries |
|
|
491 | (1) |
|
|
492 | (5) |
|
|
492 | (1) |
|
C.2.1.1 Building-block Model Purpose and Description |
|
|
492 | (1) |
|
|
493 | (1) |
|
|
493 | (1) |
|
C.2.2.1 Ideal_LD_Resonator |
|
|
493 | (1) |
|
C.2.2.2 Ideal_FE_Resonator |
|
|
493 | (1) |
|
C.2.2.3 Ideal_CT_Resonator |
|
|
493 | (1) |
|
|
494 | (1) |
|
|
494 | (1) |
|
C.2.3.2 Ideal_Comparator_for_SI |
|
|
495 | (1) |
|
C.2.3.3 Ideal_Multibit_Quantizer |
|
|
495 | (1) |
|
C.2.3.4 Ideal_Multibit_Quantizer_for_SI |
|
|
496 | (1) |
|
C.2.3.5 Ideal_Multibit_Quantizer_levels |
|
|
496 | (1) |
|
C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2 |
|
|
496 | (1) |
|
|
496 | (1) |
|
C.2.4 Ideal D/A Converters |
|
|
496 | (1) |
|
|
496 | (1) |
|
C.2.4.2 Ideal_DAC_dig_level_SD2 |
|
|
497 | (1) |
|
C.3 Real SC Building-Block Libraries |
|
|
497 | (6) |
|
C.3.1 Real SC Integrators |
|
|
497 | (4) |
|
|
501 | (2) |
|
C.4 Real SI Building-Block Libraries |
|
|
503 | (5) |
|
C.4.1 Real SI Integrators |
|
|
503 | (2) |
|
|
505 | (1) |
|
C.4.3 SI Errors and Model Parameters |
|
|
506 | (1) |
|
C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator |
|
|
506 | (1) |
|
C.4.3.2 SI_FE(LD)_Int_Finite_Conductance |
|
|
507 | (1) |
|
C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection |
|
|
508 | (1) |
|
C.5 Real CT Building-Block Libraries |
|
|
508 | (9) |
|
C.5.1 Real CT Integrators |
|
|
508 | (3) |
|
C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks |
|
|
511 | (1) |
|
C.5.1.2 Gm-MC Integrators |
|
|
511 | (1) |
|
C.5.1.3 Active-RC Integrators |
|
|
512 | (1) |
|
C.5.1.4 MOSFET-C Integrators |
|
|
513 | (1) |
|
|
513 | (1) |
|
|
514 | (3) |
|
|
517 | (1) |
|
C.6 Real Quantizers & Comparators |
|
|
517 | (1) |
|
|
518 | (1) |
|
|
519 | (4) |
Index |
|
523 | |