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E-raamat: Sigma-Delta Converters: Practical Design Guide

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  • ISBN-13: 9781119275763
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  • Formaat: EPUB+DRM
  • Sari: IEEE Press
  • Ilmumisaeg: 22-Aug-2018
  • Kirjastus: Wiley-IEEE Press
  • Keel: eng
  • ISBN-13: 9781119275763
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Thoroughly revised and expanded to help readers systematically increase their knowledge and insight about Sigma-Delta Modulators

Sigma-Delta Modulators (SDMs) have become one of the best choices for the implementation of analog/digital interfaces of electronic systems integrated in CMOS technologies. Compared to other kinds of Analog-to-Digital Converters (ADCs), Σ∆Ms cover one of the widest conversion regions of the resolution-versus-bandwidth plane, being the most efficient solution to digitize signals in an increasingly number of applications, which span from high-resolution low-bandwidth digital audio, sensor interfaces, and instrumentation, to ultra-low power biomedical systems and medium-resolution broadband wireless communications.

Following the spirit of its first edition, Sigma-Delta Converters: Practical Design Guide, 2nd Edition takes a comprehensive look at SDMs, their diverse types of architectures, circuit techniques, analysis synthesis methods, and CAD tools, as well as their practical design considerations. It compiles and updates the current research reported on the topic, and explains the multiple trade-offs involved in the whole design flow of Sigma-Delta Modulators—from specifications to chip implementation and characterization. The book follows a top-down approach in order to provide readers with the necessary understanding about recent advances, trends, and challenges in state-of-the-art Σ∆Ms. It makes more emphasis on two key points, which were not treated so deeply in the first edition:

  • It includes a more detailed explanation of Σ∆Ms implemented using Continuous-Time (CT) circuits, going from system-level synthesis to practical circuit limitations.
  • It provides more practical case studies and applications, as well as a deeper description of the synthesis methodologies and CAD tools employed in the design of Σ∆ converters.

Sigma-Delta Converters: Practical Design Guide, 2nd Edition serves as an excellent textbook for undergraduate and graduate students in electrical engineering as well as design engineers working on SD data-converters, who are looking for a uniform and self-contained reference in this hot topic. With this goal in mind, and based on the feedback received from readers, the contents have been revised and structured to make this new edition a unique monograph written in a didactical, pedagogical, and intuitive style. 

Preface xix
Acknowledgements xxv
List of Abbreviations
xxvii
1 Introduction to ΣΔ Modulators: Fundamentals, Basic Architecture and Performance Metrics
1(28)
1.1 Basics of Analog-to-Digital Conversion
2(7)
1.1.1 Sampling
3(1)
1.1.2 Quantization
4(1)
1.1.3 Quantization White Noise Model
5(3)
1.1.4 Noise Shaping
8(1)
1.2 Sigma-Delta Modulation
9(4)
1.2.1 From Noise-shaped Systems to ΣΔ Modulators
10(1)
1.2.2 Performance Metrics of ΣΔMs
11(2)
1.3 The First-order ΣΔ Modulator
13(3)
1.4 Performance Enhancement and Taxonomy of ΣΔMs
16(3)
1.4.1 ΣΔM System-level Design Parameters and Strategies
17(1)
1.4.2 Classification of ΣΔMs
18(1)
1.5 Putting All The Pieces Together: From ΣΔMs to ΣΔ ADCs
19(3)
1.5.1 Some Words about ΣΔ Decimators
20(2)
1.6 ΣΔ DACs
22(3)
1.6.1 System Design Trade-offs and Signal Processing in ΣΔ DACs
22(2)
1.6.2 Implementation of Digital ΣΔMs used in DACs
24(1)
1.7 Summary
25(4)
References
26(3)
2 Taxonomy of ΣΔ Architectures
29(54)
2.1 Second-order ΣΔ Modulators
30(5)
2.1.1 Alternative Representations of Second-order ΣΔMs
31(3)
2.1.2 Second-Order ΣΔM with Unity STF
34(1)
2.2 High-order Single-loop ΣΔM
35(4)
2.3 Cascade ΣΔ Modulators
39(10)
2.3.1 SMASH ΣΔM Architectures
46(3)
2.4 Multi-bit ΣΔ Modulators
49(6)
2.4.1 Influence of Multi-bit DAC Errors
49(1)
2.4.2 Dynamic Element Matching Techniques
50(3)
2.4.3 Dual Quantization
53(1)
2.4.3.1 Dual-quantization Single-loop ΣΔMs
53(1)
2.4.3.2 Dual-quantization Cascade ΣΔMs
54(1)
2.5 Band-pass ΣΔ Modulators
55(9)
2.5.1 Quadrature BP-ΣΔMs
56(2)
2.5.2 The z → -z2 LP--BP Transformation
58(1)
2.5.3 BP-ΣΔMs with Optimized NTF
58(3)
2.5.4 Time-interleaved and Polyphase BP-ΣΔMs
61(3)
2.6 Continuous-time ZA Modulators: Architecture and Basic Concepts
64(6)
2.6.1 An Intuitive Analysis of CT-ΣΔMs
66(3)
2.6.2 Some Words about Alias Rejection in CT-ΣΔMs
69(1)
2.7 DT--CT Transformation of ΣΔMs
70(4)
2.7.1 The Impulse-invariant Transformation
70(2)
2.7.2 DT--CT Transformation of a Second-order ΣΔM
72(2)
2.8 Direct Synthesis of CT-ΣΔMs
74(2)
2.9 Summary
76(7)
References
76(7)
3 Circuit Errors in Switched-capacitor ΣΔ Modulators
83(40)
3.1 Overview of Nonidealities in Switched-capacitor ΣΔ Modulators
84(2)
3.2 Finite Amplifier Gain in SC-ΣΔMs
86(4)
3.3 Capacitor Mismatch in SC-ΣΔMs
90(1)
3.4 Integrator Settling Error in SC-ΣΔMs
91(10)
3.4.1 Behavioral Model for the Integrator Settling
91(4)
3.4.2 Linear Effect of Finite Amplifier Gain-Bandwidth Product
95(3)
3.4.3 Nonlinear Effect of Finite Amplifier Slew Rate
98(2)
3.4.4 Effect of Finite Switch On-resistance
100(1)
3.5 Circuit Noise in SC-ΣΔ Ms
101(4)
3.6 Clock Jitter in SC-ΣΔMs
105(2)
3.7 Sources of Distortion in SC-ΣΔMs
107(4)
3.7.1 Nonlinear Amplifier Gain
107(2)
3.7.2 Nonlinear Switch On-Resistance
109(2)
3.8 Case Study: High-level Sizing of a ΣΔM
111(8)
3.8.1 Ideal Modulator Performance
111(1)
3.8.2 Noise Leakages
112(3)
3.8.3 Circuit Noise
115(1)
3.8.4 Settling Error
116(1)
3.8.5 Overall High-Level Sizing and Noise Budget
117(2)
3.9 Summary
119(4)
References
119(4)
4 Circuit Errors and Compensation Techniques in Continuous-time EA Modulators
123(42)
4.1 Overview of Nonidealities in Continuous-time ΣΔ Modulators
123(1)
4.2 CT Integrators and Resonators
124(2)
4.3 Finite Amplifier Gain in CT-ΣΔMs
126(2)
4.4 Time-constant Error in CT-ΣΔMs
128(2)
4.5 Finite Integrator Dynamics in CT-ΣΔMs
130(4)
4.5.1 Effect of Finite Gain-Bandwidth Product on CT-ΣΔMs
131(2)
4.5.2 Effect of Finite Slew Rate on CT-ΣΔMs
133(1)
4.6 Sources of Distortion in CT-ΣΔMs
134(3)
4.6.1 Nonlinearities in the Front-end Integrator
134(2)
4.6.2 Intersymbol Interference in the Feedback DAC
136(1)
4.7 Circuit Noise in CT-ΣΔMs
137(3)
4.7.1 Noise Analysis Considering NRZ Feedback DACs
137(2)
4.7.2 Noise Analysis Considering SC Feedback DACs
139(1)
4.8 Clock Jitter in CT-ΣΔMs
140(9)
4.8.1 Jitter in Return-to-zero DACs
141(1)
4.8.2 Jitter in Non-return-to-zero DACs
142(2)
4.8.3 Jitter in Switched-capacitor DACs
144(1)
4.8.4 Lingering Effect of Clock Jitter Error
145(2)
4.8.5 Reducing the Effect of Clock Jitter with FIR and Sine-shaped DACs
147(2)
4.9 Excess Loop Delay in CT-ΣΔMs
149(6)
4.9.1 Intuitive Analysis of ELD
149(2)
4.9.2 Analysis of ELD based on Impulse-invariant DT-CT Transformation
151(3)
4.9.3 Alternative ELD Compensation Techniques
154(1)
4.10 Quantizer Metastability in CT-ΣΔMs
155(4)
4.11 Summary
159(6)
References
160(5)
5 Behavioral Modeling and High-level Simulation
165(70)
5.1 Systematic Design Methodology of ΣΔ Modulators
165(4)
5.1.1 System Partitioning and Abstraction Levels
167(1)
5.1.2 Sizing Process
167(2)
5.2 Simulation Approaches for the High-level Evaluation of ΣΔMs
169(4)
5.2.1 Alternatives to Transistor-level Simulation
169(2)
5.2.2 Event-driven Behavioral Simulation Technique
171(1)
5.2.3 Programming Languages and Behavioral Modeling Platforms
172(1)
5.3 Implementing ΣΔM Behavioral Models
173(15)
5.3.1 From Circuit Analysis to Computational Algorithms
173(2)
5.3.2 Time-domain versus Frequency-domain Behavioral Models
175(3)
5.3.3 Implementing Time-domain Behavioral Models in MATLAB
178(4)
5.3.4 Building Time-domain Behavioral Models as SIMULINK C-MEX S-functions
182(6)
5.4 Efficient Behavioral Modeling of ZAM Building Blocks using C-MEX S-functions
188(21)
5.4.1 Modeling of SC Integrators using S-functions
188(2)
5.4.1.1 Capacitor Mismatch and Nonlinearity
190(1)
5.4.1.2 Input-referred Thermal Noise
191(3)
5.4.1.3 Switch On-resistance Dynamics
194(3)
5.4.1.4 Incomplete Settling Error
197(3)
5.4.2 Modeling of CT Integrators using S-functions
200(1)
5.4.2.1 Single-pole Gm-C Model
200(1)
5.4.2.2 Two-pole Dynamics Model
201(2)
5.4.2.3 Modeling Transconductors as S-functions
203(2)
5.4.3 Behavioral Modeling of Quantizers using S-functions
205(1)
5.4.3.1 Modeling Multi-level ADCs as S-functions
205(2)
5.4.3.2 Modeling Multi-level DACs as S-functions
207(2)
5.5 SIMSIDES: A SIMULINK-based Behavioral Simulator for ΣΔMs
209(7)
5.5.1 Model Libraries Included in SIMSIDES
210(1)
5.5.2 Structure of SIMSIDES and its User Interface
211(1)
5.5.2.1 Creating a New EAM Block Diagram
212(3)
5.5.2.2 Setting Model Parameters
215(1)
5.5.2.3 Simulation Analyses
215(1)
5.6 Using SIMSIDES for High-level Sizing and Verification of ΣΔMs
216(15)
5.6.1 SC Second-order Single-Bit ΣΔM
216(2)
5.6.1.1 Effect of Amplifier Finite DC Gain
218(1)
5.6.1.2 Effect of Thermal Noise
218(2)
5.6.1.3 Effect of the Incomplete Settling Error
220(1)
5.6.1.4 Cumulative Effect of All Errors
221(3)
5.6.2 CT Fifth-order Cascade 3-2 Multi-bit ΣΔM
224(3)
5.6.2.1 Effect of Nonideal Effects
227(2)
5.6.2.2 High-level Synthesis and Verification
229(2)
5.7 Summary
231(4)
References
231(4)
6 Automated Design and Optimization of ΣΔMs
235(36)
6.1 Architecture Exploration and Selection: Schreier's Toolbox
236(9)
6.1.1 Basic Functions of Schreier's Delta-Sigma Toolbox
236(2)
6.1.2 Synthesis of a Fourth-order CRFF LP/BP SC-ΣΔM with Tunable Notch
238(2)
6.1.3 Synthesis of a Fourth-order BP CT-ΣΔM with Tunable Notch
240(5)
6.2 Optimization-based High-level Synthesis of ΣΔ Modulators
245(10)
6.2.1 Combining Behavioral Simulation and Optimization
246(1)
6.2.2 Using Simulated Annealing as Optimization Engine
247(6)
6.2.3 Combining SIMSIDES with MATLAB Optimizers
253(2)
6.3 Lifting Method and Hardware Acceleration to Optimize CT-ΣΔMs
255(4)
6.3.1 Hardware Emulation of CT-ΣΔMs on an FPGA
257(1)
6.3.2 GPU-accelerated Computing of CT-ΣΔMs
258(1)
6.4 Using Multi-objective Evolutionary Algorithms to Optimize ΣΔMs
259(10)
6.4.1 Combining MOEA with SIMSIDES
261(1)
6.4.2 Applying MOEA and SIMSIDES to the Synthesis of CT-ΣΔMs
262(7)
6.5 Summary
269(2)
References
269(2)
7 Electrical Design of ΣΔMs: From Systems to Circuits
271(30)
7.1 Macromodeling ΣΔMs
272(7)
7.1.1 SC Integrator Macromodel
272(1)
7.1.1.1 Switch Macromodel
272(2)
7.1.1.2 OTA Macromodel
274(1)
7.1.2 CT Integrator Macromodel
274(1)
7.1.2.1 Active-RC Integrators
274(1)
7.1.2.2 Gm-C Integrators
274(1)
7.1.3 Nonlinear OTA Transconductor
275(1)
7.1.4 Embedded Flash ADC Macromodel
276(1)
7.1.5 Feedback DAC Macromodel
277(2)
7.2 Examples of ΣΔM Macromodels
279(7)
7.2.1 SC Second-order Example
279(4)
7.2.2 Second-order Active-RC ΣΔM
283(3)
7.3 Including Noise in Transient Electrical Simulations of ΣΔMs
286(8)
7.3.1 Generating and Injecting Noise Data Sequences in HSPICE
287(2)
7.3.2 Analyzing the Impact of the Main Noise Sources in SC Integrators
289(1)
7.3.3 Generating and Injecting Flicker Noise Sources in Electrical Simulations
289(4)
7.3.4 Test Bench to Include Noise in the Simulation of ΣΔMs
293(1)
7.4 Processing EAM Output Results of Electrical Simulations
294(4)
7.5 Summary
298(3)
References
298(3)
8 Design Considerations of ZAM Subcircuits
301(40)
8.1 Design Considerations of CMOS Switches
302(6)
8.1.1 Trade-Off Between Ron and the CMOS Switch Drain/Source Parasitic Capacitances
302(1)
8.1.2 Characterizing the Nonlinear Behavior of Ron
302(2)
8.1.3 Influence of Technology Downscaling on the Design of Switches
304(1)
8.1.4 Evaluating Harmonic Distortion due to CMOS Switches
305(3)
8.2 Design Considerations of Operational Amplifiers
308(9)
8.2.1 Typical Amplifier Topologies
309(2)
8.2.2 Common-mode Feedback Networks
311(2)
8.2.3 Characterization of the Amplifier in AC
313(1)
8.2.4 Characterization of the Amplifier in DC
313(3)
8.2.5 Characterization of the Amplifier Gain Nonlinearity
316(1)
8.3 Design Considerations of Transconductors
317(7)
8.3.1 Highly Linear Front-end Transconductor
318(2)
8.3.2 Loop-filter Transconductors
320(3)
8.3.3 Widely Programmable Transconductors
323(1)
8.4 Design Considerations of Comparators
324(8)
8.4.1 Regenerative Latch-based Comparators
325(2)
8.4.2 Design Guidelines of Comparators
327(1)
8.4.3 Characterization of Offset and Hysteresis Based on the Input-ramp Method
328(1)
8.4.4 Characterization of Offset and Hysteresis Based on the Bisectional Method
328(2)
8.4.5 Characterizing the Comparison Time
330(2)
8.5 Design Considerations of Current-Steering DACs
332(6)
8.5.1 Fundamentals and Basic Concepts of CS DACs
333(1)
8.5.2 Practical Realization of CS DACs
333(3)
8.5.3 Current Cell Circuits, Error Limitations, and Design Criteria
336(1)
8.5.4 CS 4-bit DAC Example
336(2)
8.6 Summary
338(3)
References
338(3)
9 Practical Realization of ΣΔMs: From Circuits to Chips
341(48)
9.1 Auxiliary ΣΔM Building Blocks
341(7)
9.1.1 Clock-phase Generators
342(1)
9.1.1.1 Phase Generation
342(1)
9.1.1.2 Phase Buffering
342(2)
9.1.1.3 Phase Distribution
344(1)
9.1.2 Generation of Common-mode Voltage, Reference Voltage, and Bias Currents
345(1)
9.1.2.1 Bandgap Circuit
345(1)
9.1.2.2 Reference Voltage Generator
345(1)
9.1.2.3 Master Bias Current Generator
346(1)
9.1.2.4 Common-mode Voltage Generator
346(1)
9.1.3 Additional Digital Logic
347(1)
9.2 Layout Design, Floorplanning, and Practical Issues
348(6)
9.2.1 Layout Floorplanning
348(1)
9.2.1.1 Divide Layout into Different Parts or Regions
348(1)
9.2.1.2 Shield Sensitive ΣΔM Analog Subcircuits from Switching Noise
349(1)
9.2.1.3 Buses to Distribute Signals Shared by Different EAM Pans
349(1)
9.2.1.4 Be Obsessive about Layout Symmetry and Details of Analog Parts
349(1)
9.2.2 UO Pad Ring
350(1)
9.2.3 Importance of Layout Verification and Catastrophic Failure
350(4)
9.3 Chip Package, Test PCB, and Experimental Setup
354(1)
9.3.1 Bonding Diagram and Package
354(1)
9.3.2 Test PCB
355(1)
9.4 Experimental Test Set-Up
355(4)
9.4.1 Planning the Type and Number of Instruments Needed
357(1)
9.4.2 Connecting Lab Instruments
357(1)
9.4.3 Measurement Set-Up Example
358(1)
9.5 EAM Design Examples and Case Studies
359(26)
9.5.1 Programmable-gain ΣΔMs for High Dynamic Range Sensor Interfaces
360(1)
9.5.1.1 Main Design Criteria and Performance Limitations
361(1)
9.5.1.2 SC Realization with Programmable Gain and Double Sampling
362(1)
9.5.1.3 Influence of Chopper Frequency on Flicker Noise
362(2)
9.5.2 Reconfigurable SC-ΣΔMs for Multi-standard Direct Conversion Receivers
364(3)
9.5.2.1 Power-scaling Circuit Techniques
367(1)
9.5.2.2 Experimental Results
368(1)
9.5.3 Using Widely-programmable Gm-LC BP-ΣΔMs for RF Digitizers
368(3)
9.5.3.1 Application Scenario
371(1)
9.5.3.2 Gm-LC BP-ΣΔM High-level Sizing
371(4)
9.5.3.3 BP CT-ΣΔM Loop-Filter Reconfiguration Techniques
375(3)
9.5.3.4 Embedded 4-bit Quantizer with Calibration
378(4)
9.5.3.5 Biasing, Digital Control Programmability and Testability
382(3)
9.6 Summary
385(4)
References
386(3)
10 Frontiers, Trends and Challenges: Towards Next-generation ΣΔ Modulators
389(74)
10.1 State-of-the-Art ADCs: Nyquist-rate versus ZA Converters
390(3)
10.1.1 Conversion Energy
391(1)
10.1.2 Figures of Merit
392(1)
10.2 Comparison of Different Categories of ΣΔ ADCs
393(15)
10.2.1 Aperture Plot of ΣΔMs
406(1)
10.2.2 Energy Plot of ΣΔMs
407(1)
10.3 Empirical and Statistical Analysis of State-of-the-Art ΣΔMs
408(7)
10.3.1 SC versus CT ΣΔMs
408(2)
10.3.2 Technology used in State-of-the-Art ΣΔMs
410(1)
10.3.3 Single-Loop versus Cascade ΣΔMs
410(1)
10.3.4 Single-bit versus Multi-bit ΣΔMs
411(2)
10.3.5 Low-pass versus Band-pass ΣΔMs
413(2)
10.3.6 Emerging ZAM Techniques
415(1)
10.4 Gigahertz-range ΣΔMs for RF-to-digital Conversion
415(3)
10.5 Enhanced Cascade ΣΔMs
418(5)
10.5.1 SMASH CT-ΣΔMs
418(1)
10.5.2 Two-stage 0-L MASH
419(1)
10.5.3 Stage-sharing Cascade ΣΔMs
420(1)
10.5.4 Multi-rate and Hybrid CT/DT ΣΔMs
420(1)
10.5.4.1 Upsampling Cascade MR-ΣΔMs
421(1)
10.5.4.2 Downsampling Hybrid CT/DT Cascade MR-ΣΔMs
422(1)
10.6 Power-efficient ZAM Loop-filter Techniques
423(5)
10.6.1 Inverter-based ΣΔMs
423(1)
10.6.2 Hybrid Active/Passive and Amplifier-less ΣΔMs
424(2)
10.6.3 Power-efficient Amplifier Techniques
426(2)
10.7 Hybrid ZAM/Nyquist-rate ADCs
428(3)
10.7.1 Multi-bit ZAM Quantizers based on Nyquist-rate ADCs
428(1)
10.7.2 Incremental ZA ADCs
429(2)
10.8 Time-based ZA ADCs
431(5)
10.8.1 ΣΔMs with VCO/PWM-based Quantization
432(1)
10.8.2 Scaling-friendly Mostly-digital ΣΔMs
433(1)
10.8.3 GRO-based ΣΔMs
434(2)
10.9 DAC Techniques for High-performance CT-ΣΔMs
436(1)
10.10 Classification of State-of-the-Art References
437(1)
10.11 Summary and Conclusions
437(26)
References
438(25)
A State-space Analysis of Clock Jitter in CT-ΣΔMs
463(6)
A.1 State-space Representation of NTF (z)
463(2)
A.2 Expectation Value of (Δqn)2
465(1)
A.3 In-band Noise Power due to Clock Jitter
466(3)
References
467(2)
B SIMSIDES User Guide
469(22)
B.1 Getting Started: Installing and Running SIMSIDES
470(1)
B.2 Building and Editing SAM Architectures in SIMSIDES
470(3)
B.3 Analyzing ΣΔMs in SIMSIDES
473(7)
B.3.1 Node Spectrum Analysis
474(1)
B.3.2 Integrated Power Noise
474(1)
B.3.3 SNR/SNDR
475(1)
B.3.4 Harmonic Distortion
475(2)
B.3.5 Integral and Differential Non-Linearity
477(1)
B.3.6 Multi-tone Power Ratio
477(1)
B.3.7 Histogram
478(1)
B.3.8 Parametric Analysis
478(1)
B.3.9 Monte Carlo Analysis
479(1)
B.4 Optimization Interface
480(2)
B.5 Tutorial Example: Using SIMSIDES to Model and Analyze ΣΔMs
482(7)
B 5.1 Creating the Cascade 2-1 ΣΔM Block Diagram in SIMSIDES
482(1)
B.5.2 Setting Model Parameters
482(2)
B.5.3 Computing the Output Spectrum
484(2)
B.5.4 SNR versus Input Amplitude Level
486(1)
B.5.5 Parametric Analysis Considering Only One Parameter
487(1)
B.5.6 Parametric Analysis Considering Two Parameters
488(1)
B.5.7 Computing Histograms
489(1)
B.6 Getting Help
489(2)
C SIMSIDES Block Libraries and Models
491(32)
C.1 Overview of SIMSIDES Libraries
491(1)
C.2 Ideal Libraries
492(5)
C.2.1 Ideal Integrators
492(1)
C.2.1.1 Building-block Model Purpose and Description
492(1)
C.2.1.2 Model Parameters
493(1)
C.2.2 Ideal Resonators
493(1)
C.2.2.1 Ideal_LD_Resonator
493(1)
C.2.2.2 Ideal_FE_Resonator
493(1)
C.2.2.3 Ideal_CT_Resonator
493(1)
C.2.3 Ideal Quantizers
494(1)
C.2.3.1 Ideal_Comparator
494(1)
C.2.3.2 Ideal_Comparator_for_SI
495(1)
C.2.3.3 Ideal_Multibit_Quantizer
495(1)
C.2.3.4 Ideal_Multibit_Quantizer_for_SI
496(1)
C.2.3.5 Ideal_Multibit_Quantizer_levels
496(1)
C.2.3.6 Ideal_Multibit_Quantizer_levels_SD2
496(1)
C.2.3.7 IdeaLSampler
496(1)
C.2.4 Ideal D/A Converters
496(1)
C.2.4.1 Ideal_DAC_for_SI
496(1)
C.2.4.2 Ideal_DAC_dig_level_SD2
497(1)
C.3 Real SC Building-Block Libraries
497(6)
C.3.1 Real SC Integrators
497(4)
C.3.2 Real SC Resonators
501(2)
C.4 Real SI Building-Block Libraries
503(5)
C.4.1 Real SI Integrators
503(2)
C.4.2 Real SI Resonators
505(1)
C.4.3 SI Errors and Model Parameters
506(1)
C.4.3.1 Basic_SI_FE(LD)_Integrator and Basic_SI_FE(LD)_Resonator
506(1)
C.4.3.2 SI_FE(LD)_Int_Finite_Conductance
507(1)
C.4.3.3 SI_FE(LD)_Int_Finite_Conductance & Settling & ChargeInjection
508(1)
C.5 Real CT Building-Block Libraries
508(9)
C.5.1 Real CT Integrators
508(3)
C.5.1.1 Model Parameters used in Transconductors and Gm-C Integrator Building Blocks
511(1)
C.5.1.2 Gm-MC Integrators
511(1)
C.5.1.3 Active-RC Integrators
512(1)
C.5.1.4 MOSFET-C Integrators
513(1)
C.5.2 Real CT Resonators
513(1)
C.5.2.1 Gm-C Resonators
514(3)
C.5.2.2 Gm-LC Resonators
517(1)
C.6 Real Quantizers & Comparators
517(1)
C.7 Real D/A Converters
518(1)
C.8 Auxiliary Blocks
519(4)
Index 523
José M. de la Rosa is a Professor at the Institute of Microelectronics of Seville, IMSE-CNM (CSIC, University of Seville, Spain). His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance sigma-delta converters. He has worked in a number of international research and industrial projects and has co-authored over 200 peer-reviewed conference and journal papers dealing with sigma-delta ADCs. He served as Associated Editor of the IEEE Transactions on Circuits and Systems – I: Regular Papers, as Deputy Editor in Chief of the IEEE Transactions on Circuits and Systems – II: Express Briefs, and as Distinguished Lecturer of the IEEE Circuits and Systems Society.