Muutke küpsiste eelistusi

E-raamat: SRAM Design for Wireless Sensor Networks: Energy Efficient and Variability Resilient Techniques

, ,
Teised raamatud teemal:
  • Formaat - PDF+DRM
  • Hind: 110,53 €*
  • * hind on lõplik, st. muud allahindlused enam ei rakendu
  • Lisa ostukorvi
  • Lisa soovinimekirja
  • See e-raamat on mõeldud ainult isiklikuks kasutamiseks. E-raamatuid ei saa tagastada.
SRAM Design for Wireless Sensor Networks: Energy Efficient and Variability Resilient TechniquesSuurem pilt
Teised raamatud teemal:

DRM piirangud

  • Kopeerimine (copy/paste):

    ei ole lubatud

  • Printimine:

    ei ole lubatud

  • Kasutamine:

    Digitaalõiguste kaitse (DRM)
    Kirjastus on väljastanud selle e-raamatu krüpteeritud kujul, mis tähendab, et selle lugemiseks peate installeerima spetsiaalse tarkvara. Samuti peate looma endale  Adobe ID Rohkem infot siin. E-raamatut saab lugeda 1 kasutaja ning alla laadida kuni 6'de seadmesse (kõik autoriseeritud sama Adobe ID-ga).

    Vajalik tarkvara
    Mobiilsetes seadmetes (telefon või tahvelarvuti) lugemiseks peate installeerima selle tasuta rakenduse: PocketBook Reader (iOS / Android)

    PC või Mac seadmes lugemiseks peate installima Adobe Digital Editionsi (Seeon tasuta rakendus spetsiaalselt e-raamatute lugemiseks. Seda ei tohi segamini ajada Adober Reader'iga, mis tõenäoliselt on juba teie arvutisse installeeritud )

    Seda e-raamatut ei saa lugeda Amazon Kindle's. 

This book features various, ultra low energy, variability resilient SRAM circuit design techniques for wireless sensor network applications. Conventional SRAM design targets area efficiency and high performance at the increased cost of energy consumption, making it unsuitable for computation-intensive sensor node applications. This book, therefore, guides the reader through different techniques at the circuit level for reducing energy consumption and increasing the variability resilience. It includes a detailed review of the most efficient circuit design techniques and trade-offs, introduces new memory architecture techniques, sense amplifier circuits and voltage optimization methods for reducing the impact of variability for the advanced technology nodes.

This reviews the most efficient circuit design techniques and trade-offs, and introduces new memory architecture techniques, sense amplifier circuits and voltage optimization methods for reducing the impact of variability in wireless sensor applications.
1 Introduction
1(8)
1.1 Motivation and Objectives
1(2)
1.2 Traditional SRAM Design and Technology Scaling
3(2)
1.3 Structure of the Text
5(4)
References
7(2)
2 SRAM Bit Cell Optimization
9(22)
2.1 Introduction
9(3)
2.2 Different Cell Topologies
12(15)
2.2.1 Read SNM Free (RSNF) 7T Cell
13(1)
2.2.2 Differential Data Aware Power-Supplied (D2AP) 8T SRAM Cell: Improved Write Margin and Half-Select Accesses
13(1)
2.2.3 Half Select Condition Free Cross Point 8T (CR8T) SRAM Cell
14(2)
2.2.4 Read Decoupled 8T and 10T Cell (Isolation of the Internal Storage Nodes from the Read Bit-Lines)
16(8)
2.2.5 Differential Read Decoupled 8T and 10T SRAM Cells
24(3)
2.3 Summary
27(4)
References
30(1)
3 Adaptive Voltage Optimization Techniques: Low Voltage SRAM Operation
31(36)
3.1 Introduction
31(2)
3.2 WRITE Assist Techniques
33(6)
3.3 READ Assist Techniques
39(4)
3.4 Comparative Analysis
43(7)
3.5 Hybrid Voltage Optimization Techniques
50(12)
3.5.1 Crosshairs SRAM---Separately Tuning VDD and GND Supplies of SRAM Cells
52(1)
3.5.2 Configurable Write Assist: Compatibility with a Dynamic Voltage Scaling
52(1)
3.5.3 MNBL Technique: Sequential Voltage Optimization
53(7)
3.5.4 Compounded Differential VSS (CDVSS) Bias Technique
60(2)
3.6 Summary
62(5)
References
64(3)
4 Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry
67(28)
4.1 Introduction
67(1)
4.2 Hierarchical Divided Bit-Lines
68(2)
4.3 Hierarchical Divided Bit-Lines with Local Assist Circuitry
70(4)
4.3.1 Fine Grained Bit-Line Architecture
71(1)
4.3.2 Divided Read Bit-Line and Read End Detecting Replica Circuit
72(1)
4.3.3 Short Buffered Local Bit-Lines with Low Swing GBLs
73(1)
4.4 WRITE After READ Based Assist Circuitry for Enabling VDDmin Operation
74(1)
4.4.1 WRITE After READ Based Assist Circuitry
74(1)
4.4.2 Short Buffered Bit-line
74(1)
4.4.3 Low-Energy Disturb Mitigation (Half Select Issues) Scheme
75(1)
4.5 Low Swing Bit-Line Hierarchy: Enhanced SRAM Cell Stability
75(4)
4.5.1 Pseudo 8T Sensing Enabled Local Assist Circuitry
76(1)
4.5.2 Hierarchical Buffered Segmented Bit-Lines
77(2)
4.6 High Bit Density Based Bit-Line Hierarchy
79(4)
4.6.1 Cascaded Bit-Line with Self-Write-Back Sense Amplifier
79(2)
4.6.2 SRAM Cell Type Local Assist Circuitry
81(2)
4.7 Comparative Analysis
83(10)
4.7.1 Performance
83(3)
4.7.2 Stability Analysis
86(2)
4.7.3 Energy Consumption
88(2)
4.7.4 Area Overhead
90(3)
4.8 Conclusion
93(2)
References
93(2)
5 SRAM Energy Reduction Techniques
95(28)
5.1 SRAM Array Leakage Reduction
95(7)
5.1.1 Leakage Compensation-Based Techniques
96(2)
5.1.2 Leakage CutOff Based Techniques
98(4)
5.2 Dynamic WRITE Energy Reduction
102(9)
5.2.1 Write Replica Circuit for Low Power Operation
105(1)
5.2.2 Charge Recycling SRAM
105(1)
5.2.3 Sense Amplifying SRAM Cell (SAC-SRAM)
106(1)
5.2.4 Low Swing WRITE Operation
107(1)
5.2.5 Low Swing WRITE with WRITE Masking
107(2)
5.2.6 Low Swing Static WRITE operation
109(2)
5.2.7 Litho Optimized Low Swing Static WRITE
111(1)
5.3 Low Energy READ Operation
111(5)
5.3.1 Hierarchical Buffered Bit-lines
112(1)
5.3.2 Pseudo 8T Architecture Based Local Architecture
113(2)
5.3.3 RSDVt 8T SRAM: Variability Resilient Low Energy Solution
115(1)
5.4 Compartive Analysis
116(3)
5.5 Summary
119(4)
References
120(3)
6 Variation Tolerant Low Power Sense Amplifiers
123(20)
6.1 Introduction: Energy-Offset Trade off Problem in Sense Amplifier Circuits
123(3)
6.2 Calibration Based Techniques
126(4)
6.2.1 Sense Amplifier Redundancy
126(1)
6.2.2 Sense Amplifier Tuning
126(1)
6.2.3 Capacitive Resist Implementation and Parallel Device Assist Implementation
127(1)
6.2.4 Hot Carrier Injection Trimming
128(1)
6.2.5 Multi-Sized SA Redundancy
128(2)
6.3 Charge Limited Sequential Sense Amplifier: Calibration Free Solution
130(9)
6.3.1 Limitations with the Calibration Based SA Design
131(1)
6.3.2 Charge Limited Sequential Sensing: Concept
131(2)
6.3.3 Circuit Implementation
133(5)
6.3.4 Operation
138(1)
6.4 Comparison
139(1)
6.5 Conclusion
140(3)
References
141(2)
7 Prototypes
143(20)
7.1 Introduction
143(1)
7.2 IM_90 (First Prototype 90 nm IP)
143(8)
7.2.1 Target Application
143(1)
7.2.2 Design Innovation Contributions
144(1)
7.2.3 Design Description
144(6)
7.2.4 Measurement Results
150(1)
7.3 IM_65 (Second Prototype 65 nm LP)
151(7)
7.3.1 Target Application
151(1)
7.3.2 Design Innovation Contributions
152(1)
7.3.3 Design Description
153(2)
7.3.4 Measurement Results
155(3)
7.4 Comparison with the State-of-the-Art
158(5)
References
161(2)
8 Conclusions
163
8.1 Synopsys of Contribution
163(3)
8.2 Technology Scaling Perspective
166(1)
8.3 Conclusion
167(1)
8.4 Future Directions
168
References
170
Lisainfo e-raamatute kohta Lisainfo e-raamatute kohta
Püsilink: https://www.kriso.ee/db/97814614403902e.html
Märksõnad: