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E-raamat: Strain-Engineered MOSFETs

  • Formaat: 320 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781466503472
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  • Formaat: 320 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781466503472
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"This book brings together new developments in the area of spin-engineered MOSFETs using high-mobility substrates such as SIGe, strained-Si, germanium-on-insulator, and III-V semiconductors. The authors cover the materials aspects, principles, design, fabrication, and applications of advanced devices. They present a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization"--



Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale.

This book focuses on recent developments in strain-engineered MOSFETS implemented in high-mobility substrates such as, Ge, SiGe, strained-Si, ultrathin germanium-on-insulator platforms, combined with high-k insulators and metal-gate. It covers the materials aspects, principles, and design of advanced devices, fabrication, and applications. It also presents a full technology computer aided design (TCAD) methodology for strain-engineering in Si-CMOS technology involving data flow from process simulation to process variability simulation via device simulation and generation of SPICE process compact models for manufacturing for yield optimization.

Microelectronics fabrication is facing serious challenges due to the introduction of new materials in manufacturing and fundamental limitations of nanoscale devices that result in increasing unpredictability in the characteristics of the devices. The down scaling of CMOS technologies has brought about the increased variability of key parameters affecting the performance of integrated circuits. This book provides a single text that combines coverage of the strain-engineered MOSFETS and their modeling using TCAD, making it a tool for process technology development and the design of strain-engineered MOSFETs.

Arvustused

" an immensely useful book for the researcher in this field and even for some like me who do not work exactly in this area. Any scientist interested in strain modulation of device properties will value this book." Supriyo Bandyopadhyay, Virginia Commonwealth University

" a timely bridge from the conventional MOSFETs to advanced strain-engineered MOSFETs to non-classical multiple gate devices to FinFETs. I strongly recommend this book." Dr. Enrique MIRANDA, Universitat Autònoma de Barcelona

Preface ix
About the Authors xi
List of Abbreviations
xiii
List of Symbols
xvii
1 Introduction
1(14)
1.1 Technology Scaling
4(1)
1.2 Substrate-Induced Strain Engineering
5(1)
1.3 Process-Induced Stress Engineering
5(2)
1.4 Electronic Properties of Strained Semiconductors
7(1)
1.5 Strain-Engineered MOSFETs
7(1)
1.6 Noise in Strain-Engineered Devices
8(1)
1.7 Technology CAD of Strain-Engineered MOSFETs
8(2)
1.8 Reliability of Strain-Engineered MOSFETs
10(1)
1.9 Process Compact Modelling
10(1)
1.10 Process-Aware Design
11(1)
1.11 Summary
12(3)
Additional Reading
13(2)
2 Substrate-Induced Strain Engineering in CMOS Technology
15(38)
2.1 Substrate Engineering
16(2)
2.2 Strained SiGe Film Growth
18(3)
2.3 Strained SiGe:C Film Growth
21(1)
2.4 Strained Si Films on Relaxed Si1-xGex
22(3)
2.5 Strained Si on SOI
25(2)
2.6 Strained Ge Film Growth
27(2)
2.7 Strained Ge MOSFETs
29(3)
2.8 Heterostructure SiGe/SiGe:C Channel MOSFETs
32(8)
2.8.1 Band Alignment
33(2)
2.8.2 Mobility Enhancement
35(1)
2.8.3 Double Quantum Well p-MOSFETs
36(4)
2.9 Strained Si MOSFETs
40(4)
2.10 Hybrid Orientation Technology
44(6)
2.10.1 Device Simulation
45(5)
2.11 Summary
50(3)
Review Questions
51(1)
References
52(1)
3 Process-Induced Stress Engineering in CMOS Technology
53(34)
3.1 Stress Engineering
55(2)
3.2 Si1-xGex in Source/Drain
57(5)
3.3 Si1-yCy in Source/Drain
62(1)
3.4 Shallow Trench Isolation (STI)
63(1)
3.5 Contact Etch Stop Layer (CESL)
64(3)
3.6 Silicidation
67(1)
3.7 Stress Memorisation Technique (SMT)
68(1)
3.8 Global vs. Local Strain
69(2)
3.9 BEOL Stress: Through-Silicon Via
71(7)
3.10 TSV Modelling
78(6)
3.11 Summary
84(3)
Review Questions
84(1)
References
85(2)
4 Electronic Properties of Strain-Engineered Semiconductors
87(28)
4.1 Basics of Stress Engineering
89(1)
4.1.1 Stress
89(1)
4.2 Stress-Strain Relationships
90(1)
4.2.1 Modelling of Stress Generation
91(1)
4.3 Strain-Engineered MOSFETs: Current
91(2)
4.4 Energy Gap and Band Structure
93(1)
4.4.1 Bulk Si Band Structure
93(1)
4.5 Silicon Conduction Band
94(1)
4.6 Silicon Valence Band
95(1)
4.7 Band Structure under Stress
96(4)
4.8 Piezoresistive Mobility Model
100(3)
4.9 Strain-Induced Mobility Model
103(7)
4.9.1 Strain-Induced Mobility Model under Electron-Phonon Interaction
104(1)
4.9.2 Strain-Induced Interaction Potential Scattering by Acoustic Phonon
104(2)
4.9.3 Transition Probability for Acoustic Phonon Scattering
106(1)
4.9.4 Strain-Induced Scattering Matrix
107(1)
4.9.5 Relaxation Time for Acoustic Phonon Scattering
108(2)
4.10 Implementation of Mobility Model
110(1)
4.11 Summary
111(4)
Review Questions
111(1)
References
112(3)
5 Strain-Engineered MOSFETs
115(28)
5.1 Process Integration
118(4)
5.1.1 Power Consumption
118(1)
5.1.2 Leakage Current
119(1)
5.1.3 Metal Gate Electrodes
120(1)
5.1.4 High-k Gate Dielectrics
121(1)
5.2 Multigate Transistors
122(1)
5.3 Double-Gate MOSFET
123(2)
5.4 Ω-FinFET
125(2)
5.5 Tri-Gate FinFET
127(2)
5.6 FinFETs Using Gate-Induced Stress
129(4)
5.7 Stress-Engineered FinFETs
133(5)
5.8 Layout Dependence
138(3)
5.9 Summary
141(2)
Review Questions
141(1)
References
141(2)
6 Noise in Strain-Engineered Devices
143(62)
C. Mukherjee
6.1 Noise Mechanisms
146(1)
6.2 Fundamental Noise Sources
147(7)
6.2.1 Thermal Noise
147(1)
6.2.2 Shot Noise
147(1)
6.2.3 Generation-Recombination Noise
148(1)
6.2.4 Random Telegraph Signal (RTS) Noise
149(2)
6.2.5 1/f Noise
151(3)
6.3 1/f Noise in MOSFETs
154(5)
6.3.1 Number Fluctuations
154(4)
6.3.2 Mobility Fluctuations
158(1)
6.4 Noise Characterisation in MOSFETs
159(3)
6.4.1 Noise Measurements as a Diagnostic Tool
159(3)
6.5 Strain Effects on Noise in MOSFETs
162(9)
6.5.1 n-MOSFET under Tensile Stress
162(1)
6.5.2 n-MOSFET under Compressive Stress
163(1)
6.5.3 p-MOSFET under Compressive Stress
163(4)
6.5.4 Number Fluctuation Model under Strain
167(1)
6.5.4.1 Mechanisms for Change in Noise PSD under Strain
167(4)
6.6 Noise in Strain-Engineered MOSFETs
171(10)
6.6.1 Low-Frequency Noise Measurements
172(1)
6.6.2 Strained Si MOSFETs
173(8)
6.7 Noise in Multigate FETs
181(6)
6.7.1 Noise in Tri-Gate FinFET
182(5)
6.8 Noise in Silicon Nanowire Transistors (SNWTs)
187(4)
6.9 Noise in Heterojunction Bipolar Transistors
191(9)
6.9.1 Low-Frequency Noise Measurement of SiGe:C HBT
192(8)
6.10 Summary
200(5)
Review Questions
201(1)
References
202(3)
7 Technology CAD of Strain-Engineered MOSFETs
205(24)
7.1 TCAD Calibration
206(2)
7.2 Simulation of Strain-Engineered MOSFETs
208(7)
7.2.1 Strain-Engineered p-MOSFETs
210(2)
7.2.2 Strain-Engineered n-MOSFETs
212(3)
7.3 DC Performance
215(5)
7.4 AC Performance
220(1)
7.5 Hybrid Orientation Technology for Strain-Engineered MOSFETs
220(4)
7.6 Simulation of Embedded SiGe MOSFETs
224(2)
7.7 Summary
226(3)
Review Questions
226(1)
References
227(2)
8 Reliability and Degradation of Strain-Engineered MOSFETs
229(20)
8.1 NBTI in Strain-Engineered p-MOSFETs
231(4)
8.1.1 Quasi-2D Coulomb Mobility Model
232(3)
8.2 Simulation of NBTI in p-MOSFETs
235(2)
8.3 HCI in Strain-Engineered n-MOSFETs
237(1)
8.3.1 Degradation Mechanisms
237(1)
8.4 Simulation of HCI in n-MOSFETs
238(4)
8.5 Reliability Issues in FinFETs
242(4)
8.6 Summary
246(3)
Review Questions
247(1)
References
247(2)
9 Process Compact Modelling of Strain-Engineered MOSFETs
249(24)
9.1 Process Variation
250(1)
9.2 Predictive Technology Modelling
251(8)
9.2.1 PTM for FinFET
259(1)
9.3 Process-Aware Design for Manufacturing
259(2)
9.4 Process Compact Model
261(4)
9.4.1 PCM Analysis
264(1)
9.5 Process-Aware SPICE Parameter Extraction
265(4)
9.5.1 Circuit Modelling
268(1)
9.6 Summary
269(4)
Review Questions
270(1)
References
271(2)
10 Process-Aware Design of Strain-Engineered MOSFETs
273(14)
10.1 Process Design Co-Optimisation
274(1)
10.2 Classifications of Variation
275(2)
10.3 Designs for Manufacturing and Yield Optimisation
277(4)
10.3.1 Process Optimisation
278(1)
10.3.2 Process Parameterisation
278(1)
10.3.3 Smoothness and Sensitivity Analysis
279(1)
10.3.4 Visual Optimisation
280(1)
10.4 Performance Optimisation
281(1)
10.5 Manufacturability Optimisation
282(3)
10.6 Summary
285(2)
Review Questions
285(1)
References
286(1)
11 Conclusions
287(2)
Index 289
C K Maiti (Author) ,  T K Maiti (Indian Institute of Technology, Kharagpur, India Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur Indian Institute of Technology, Kharagpur) (Author)