Preface |
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ix | |
About the Authors |
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xi | |
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xiii | |
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xvii | |
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1 | (14) |
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4 | (1) |
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1.2 Substrate-Induced Strain Engineering |
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5 | (1) |
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1.3 Process-Induced Stress Engineering |
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5 | (2) |
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1.4 Electronic Properties of Strained Semiconductors |
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7 | (1) |
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1.5 Strain-Engineered MOSFETs |
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7 | (1) |
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1.6 Noise in Strain-Engineered Devices |
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8 | (1) |
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1.7 Technology CAD of Strain-Engineered MOSFETs |
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8 | (2) |
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1.8 Reliability of Strain-Engineered MOSFETs |
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10 | (1) |
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1.9 Process Compact Modelling |
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10 | (1) |
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1.10 Process-Aware Design |
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11 | (1) |
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12 | (3) |
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13 | (2) |
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2 Substrate-Induced Strain Engineering in CMOS Technology |
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15 | (38) |
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2.1 Substrate Engineering |
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16 | (2) |
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2.2 Strained SiGe Film Growth |
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18 | (3) |
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2.3 Strained SiGe:C Film Growth |
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21 | (1) |
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2.4 Strained Si Films on Relaxed Si1-xGex |
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22 | (3) |
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25 | (2) |
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2.6 Strained Ge Film Growth |
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27 | (2) |
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29 | (3) |
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2.8 Heterostructure SiGe/SiGe:C Channel MOSFETs |
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32 | (8) |
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33 | (2) |
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2.8.2 Mobility Enhancement |
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35 | (1) |
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2.8.3 Double Quantum Well p-MOSFETs |
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36 | (4) |
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40 | (4) |
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2.10 Hybrid Orientation Technology |
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44 | (6) |
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45 | (5) |
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50 | (3) |
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51 | (1) |
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52 | (1) |
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3 Process-Induced Stress Engineering in CMOS Technology |
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53 | (34) |
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55 | (2) |
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3.2 Si1-xGex in Source/Drain |
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57 | (5) |
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3.3 Si1-yCy in Source/Drain |
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62 | (1) |
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3.4 Shallow Trench Isolation (STI) |
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63 | (1) |
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3.5 Contact Etch Stop Layer (CESL) |
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64 | (3) |
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67 | (1) |
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3.7 Stress Memorisation Technique (SMT) |
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68 | (1) |
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3.8 Global vs. Local Strain |
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69 | (2) |
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3.9 BEOL Stress: Through-Silicon Via |
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71 | (7) |
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78 | (6) |
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84 | (3) |
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84 | (1) |
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85 | (2) |
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4 Electronic Properties of Strain-Engineered Semiconductors |
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87 | (28) |
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4.1 Basics of Stress Engineering |
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89 | (1) |
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89 | (1) |
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4.2 Stress-Strain Relationships |
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90 | (1) |
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4.2.1 Modelling of Stress Generation |
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91 | (1) |
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4.3 Strain-Engineered MOSFETs: Current |
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91 | (2) |
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4.4 Energy Gap and Band Structure |
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93 | (1) |
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4.4.1 Bulk Si Band Structure |
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93 | (1) |
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4.5 Silicon Conduction Band |
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94 | (1) |
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95 | (1) |
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4.7 Band Structure under Stress |
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96 | (4) |
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4.8 Piezoresistive Mobility Model |
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100 | (3) |
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4.9 Strain-Induced Mobility Model |
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103 | (7) |
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4.9.1 Strain-Induced Mobility Model under Electron-Phonon Interaction |
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104 | (1) |
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4.9.2 Strain-Induced Interaction Potential Scattering by Acoustic Phonon |
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104 | (2) |
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4.9.3 Transition Probability for Acoustic Phonon Scattering |
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106 | (1) |
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4.9.4 Strain-Induced Scattering Matrix |
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107 | (1) |
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4.9.5 Relaxation Time for Acoustic Phonon Scattering |
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108 | (2) |
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4.10 Implementation of Mobility Model |
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110 | (1) |
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111 | (4) |
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111 | (1) |
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112 | (3) |
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5 Strain-Engineered MOSFETs |
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115 | (28) |
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118 | (4) |
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118 | (1) |
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119 | (1) |
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5.1.3 Metal Gate Electrodes |
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120 | (1) |
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5.1.4 High-k Gate Dielectrics |
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121 | (1) |
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5.2 Multigate Transistors |
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122 | (1) |
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123 | (2) |
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125 | (2) |
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127 | (2) |
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5.6 FinFETs Using Gate-Induced Stress |
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129 | (4) |
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5.7 Stress-Engineered FinFETs |
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133 | (5) |
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138 | (3) |
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141 | (2) |
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141 | (1) |
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141 | (2) |
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6 Noise in Strain-Engineered Devices |
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143 | (62) |
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146 | (1) |
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6.2 Fundamental Noise Sources |
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147 | (7) |
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147 | (1) |
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147 | (1) |
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6.2.3 Generation-Recombination Noise |
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148 | (1) |
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6.2.4 Random Telegraph Signal (RTS) Noise |
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149 | (2) |
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151 | (3) |
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154 | (5) |
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6.3.1 Number Fluctuations |
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154 | (4) |
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6.3.2 Mobility Fluctuations |
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158 | (1) |
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6.4 Noise Characterisation in MOSFETs |
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159 | (3) |
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6.4.1 Noise Measurements as a Diagnostic Tool |
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159 | (3) |
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6.5 Strain Effects on Noise in MOSFETs |
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162 | (9) |
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6.5.1 n-MOSFET under Tensile Stress |
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162 | (1) |
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6.5.2 n-MOSFET under Compressive Stress |
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163 | (1) |
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6.5.3 p-MOSFET under Compressive Stress |
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163 | (4) |
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6.5.4 Number Fluctuation Model under Strain |
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167 | (1) |
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6.5.4.1 Mechanisms for Change in Noise PSD under Strain |
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167 | (4) |
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6.6 Noise in Strain-Engineered MOSFETs |
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171 | (10) |
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6.6.1 Low-Frequency Noise Measurements |
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172 | (1) |
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6.6.2 Strained Si MOSFETs |
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173 | (8) |
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6.7 Noise in Multigate FETs |
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181 | (6) |
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6.7.1 Noise in Tri-Gate FinFET |
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182 | (5) |
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6.8 Noise in Silicon Nanowire Transistors (SNWTs) |
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187 | (4) |
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6.9 Noise in Heterojunction Bipolar Transistors |
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191 | (9) |
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6.9.1 Low-Frequency Noise Measurement of SiGe:C HBT |
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192 | (8) |
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200 | (5) |
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201 | (1) |
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202 | (3) |
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7 Technology CAD of Strain-Engineered MOSFETs |
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205 | (24) |
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206 | (2) |
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7.2 Simulation of Strain-Engineered MOSFETs |
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208 | (7) |
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7.2.1 Strain-Engineered p-MOSFETs |
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210 | (2) |
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7.2.2 Strain-Engineered n-MOSFETs |
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212 | (3) |
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215 | (5) |
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220 | (1) |
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7.5 Hybrid Orientation Technology for Strain-Engineered MOSFETs |
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220 | (4) |
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7.6 Simulation of Embedded SiGe MOSFETs |
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224 | (2) |
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226 | (3) |
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226 | (1) |
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227 | (2) |
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8 Reliability and Degradation of Strain-Engineered MOSFETs |
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229 | (20) |
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8.1 NBTI in Strain-Engineered p-MOSFETs |
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231 | (4) |
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8.1.1 Quasi-2D Coulomb Mobility Model |
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232 | (3) |
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8.2 Simulation of NBTI in p-MOSFETs |
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235 | (2) |
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8.3 HCI in Strain-Engineered n-MOSFETs |
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237 | (1) |
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8.3.1 Degradation Mechanisms |
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237 | (1) |
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8.4 Simulation of HCI in n-MOSFETs |
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238 | (4) |
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8.5 Reliability Issues in FinFETs |
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242 | (4) |
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246 | (3) |
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247 | (1) |
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247 | (2) |
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9 Process Compact Modelling of Strain-Engineered MOSFETs |
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249 | (24) |
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250 | (1) |
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9.2 Predictive Technology Modelling |
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251 | (8) |
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259 | (1) |
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9.3 Process-Aware Design for Manufacturing |
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259 | (2) |
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9.4 Process Compact Model |
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261 | (4) |
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264 | (1) |
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9.5 Process-Aware SPICE Parameter Extraction |
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265 | (4) |
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268 | (1) |
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269 | (4) |
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270 | (1) |
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271 | (2) |
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10 Process-Aware Design of Strain-Engineered MOSFETs |
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273 | (14) |
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10.1 Process Design Co-Optimisation |
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274 | (1) |
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10.2 Classifications of Variation |
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275 | (2) |
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10.3 Designs for Manufacturing and Yield Optimisation |
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277 | (4) |
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10.3.1 Process Optimisation |
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278 | (1) |
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10.3.2 Process Parameterisation |
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278 | (1) |
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10.3.3 Smoothness and Sensitivity Analysis |
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279 | (1) |
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10.3.4 Visual Optimisation |
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280 | (1) |
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10.4 Performance Optimisation |
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281 | (1) |
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10.5 Manufacturability Optimisation |
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282 | (3) |
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285 | (2) |
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285 | (1) |
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286 | (1) |
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287 | (2) |
Index |
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289 | |