Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed—combined with extensive experimental validation—collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern.The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots.Defines new complex, sustainable network-on-chip architectures to reduce network latency and energyDevelops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniquesDescribes joint strategies for network- and core-level sustainabilityDiscusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures
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This instructive book focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures to create a sustainable NoC platform for future many-core chips
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1 | (10) |
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The Network-on-Chip Paradigm |
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1 | (1) |
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Traditional NoC Interconnect Topologies |
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5 | (3) |
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8 | (1) |
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9 | (2) |
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Chapter 2 Current Research Trends and State-of-the-Art NoC Designs |
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The Small-World Topology (and Other Irregular Topologies) |
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11 | (3) |
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Design for Topology-Agnostic Routing for Irregular Networks |
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14 | (1) |
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3D, Optical, and Wireless Integration for NoC |
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15 | (4) |
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Power- and Temperature-Aware Design Considerations |
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19 | (1) |
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20 | (3) |
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Chapter 3 Complex Network Inspired NoC Architecture |
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23 | (14) |
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Distance Between Cores (lij) |
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23 | (1) |
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Frequency of Interaction Between Cores (fij) |
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24 | (1) |
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Fij for Various Traffic Patterns |
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26 | (4) |
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The Small-World Characteristic |
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30 | (2) |
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32 | (1) |
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Appendix A.1 Lij Matrix for a 16 Core NoC with a Tile Floorplan |
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Appendix A.2 Fij Matrix for Uniform Random Traffic |
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Appendix A.3 Fij Matrix for Transpose Traffic |
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35 | (1) |
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Appendix A.4 Fij Matrix for Hotspot Traffic |
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36 | (1) |
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Chapter 4 Wireless Small-World NoCs |
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37 | (10) |
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Wireless Physical Layer Design |
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37 | (3) |
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Communication and Channelization |
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40 | (2) |
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Topology of Wireless NoCs |
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42 | (2) |
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44 | (3) |
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Chapter 5 Topology-Agnostic Routing for Irregular Networks |
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47 | (10) |
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A Simple Approach to Topology-Agnostic Routing |
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47 | (1) |
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Routing Strategy for Hierarchical Wireless Small-World Networks |
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48 | (1) |
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Advanced Routing Strategies for Wireless Small-World Networks |
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49 | (7) |
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56 | (1) |
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Chapter 6 Performance Evaluation and Design Trade-Offs of Wireless SWNoCs |
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57 | (22) |
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60 | (1) |
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Optimal Configuration of the SWNoC |
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60 | (2) |
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62 | (6) |
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Energy Dissipation for CSWNoC |
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68 | (1) |
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Packet Latency and Energy Dissipation of mSWNoC |
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69 | (8) |
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77 | (2) |
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Chapter 7 Dynamic Voltage and Frequency Scaling |
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79 | (28) |
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79 | (2) |
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81 | (5) |
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86 | (19) |
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105 | (2) |
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Chapter 8 Dynamic Thermal Management |
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107 | (20) |
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Temperature-Aware Task Allocation |
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107 | (3) |
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Temperature-Aware Adaptive Routing |
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110 | (3) |
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113 | (12) |
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125 | (2) |
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Chapter 9 Joint DTM and DVFS Techniques |
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127 | (16) |
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Enhanced Routing and Dynamic Thermal Management |
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127 | (1) |
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128 | (3) |
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131 | (10) |
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141 | (2) |
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Chapter 10 Conclusions and Possible Future Explorations |
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Design of 3D Wireless Small-World NoCs |
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143 | (1) |
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144 | (10) |
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154 | (1) |
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Jacob A. Murray received his PhD in Electrical and Computer Engineering at the School of Electrical Engineering and Computer Science, Washington State University in 2014 and received his BS in Computer Engineering at Washington State University in 2010. He is a Clinical Assistant Professor and Program Coordinator at the School of Electrical Engineering and Computer Science, Washington State University, Everett. His current research interests include sustainable and low-power design for on-chip interconnection networks, routing for wireless on-chip communication networks, and temperature-aware design for topology-agnostic networks. He has been a Harold Frank Entrepreneur and participated as one of five undergraduate finalist teams in the 2010 National Collegiate Inventors Competition. He is a member of Tau Beta Pi, the national engineering honors society, and a member of the IEEE. Paul Wettin received his PhD in Electrical and Computer Engineering at the School of Electrical Engineering and Computer Science, Washington State University in 2014 and received his BS in Computer Engineering at Washington State University in 2010. He is a Senior ASIC Design Engineer at Marvell Semiconductor Inc., Boise. His current research interests include wireless Network-on-Chip architectures, specifically low-power architectures that use DVFS and DTM techniques to reduce chip temperature. He is a member of Tau Beta Pi, the national engineering honors society, and a member of the IEEE. Partha Pratim Pande received the M.S. degree in computer science from the National University of Singapore and the Ph.D. degree in electrical and computer engineering from the University of British Columbia, Vancouver, BC, Canada. He is an Associate Professor at the School of Electrical Engineering and Computer Science, Washington State University, Pullman. His current research interests are novel interconnect architectures for multicore chips, on-chip wireless communication networks, and hardware accelerators for biocomputing. He has more than 60 publications on this topic in reputed journals and conferences. He is the Guest Editor of a special issue on sustainable and green computing systems for ACM Journal on Emerging Technologies in Computing Systems. Dr. Pande currently serves on the Editorial Board of IEEE Design and Test of Computers and Sustainable Computing: Informatics and Systems (SUSCOM). He also serves in the program committee of many reputed international conferences. Behrooz A. Shirazi is the Huie-Rogers Chair Professor and the Director of the School of Electrical Engineering and Computer Science at Washington State University. Dr. Shirazi has conducted research in the areas of sustainable computing, pervasive computing, software tools, distributed real-time systems, and parallel and distributed systems over the past eighteen years. He is currently serving as the Editor-in-Chief for Special Issues for the Pervasive and Mobile Computing (PMC) Journal and the Sustainable Computing (SUSCOM) Journal. He has served on the editorial boards of the IEEE Transactions on Computers and Journal of Parallel and Distributed Computing in the past. He is a co-founder of the International Green Computing Conference.
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