Preface |
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ix | |
List of Contributors |
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xiii | |
Acknowledgements |
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xv | |
1 Synchronization, Arbitration and Choice |
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1 | |
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1 | |
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1.2 The Problem of Choice |
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2 | |
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1.3 Choice in Electronics |
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3 | |
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5 | |
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1.5 Continuous and Discrete Quantities |
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6 | |
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7 | |
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9 | |
Part I |
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11 | |
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2 Modelling Metastability |
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13 | |
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14 | |
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21 | |
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23 | |
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2.3.1 Event Histograms and MTBF |
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28 | |
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2.4 Latches and Flip-flops |
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3.1 Latches and Metastability Filters |
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3.3.1 Jamb Latch Flip-flop |
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4.2 Effect of Noise on a Synchronizer |
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4.3.1 Synchronous Systems |
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63 | |
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4.3.2 Asynchronous Systems |
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66 | |
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5 Metastability Measurements |
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5.2 Synchronizer Flip-flop Testing |
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75 | |
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5.3 Rising and Falling Edges |
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5.4 Delay-based Measurement |
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5.6 Back Edge Measurement |
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5.7.1 Failure Measurement |
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5.7.2 Synchronizer Selection |
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101 | |
Part II |
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103 | |
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7 Synchronizers in Systems |
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7.1 Latency and Throughput |
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108 | |
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7.3 Avoiding Synchronization |
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110 | |
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7.4 Predictive Synchronizers |
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113 | |
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7.5 Other Low-latency Synchronizers |
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115 | |
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7.5.1 Locally Delayed Latching (LDL) |
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115 | |
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7.5.2 Speculative Synchronization |
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118 | |
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7.6 Asynchronous Communication Mechanisms (ACM) |
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125 | |
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128 | |
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7.6.2 Three-slot Mechanism |
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128 | |
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7.6.3 Four-slot Mechanism |
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130 | |
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7.6.4 Hardware Design and Metastability |
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132 | |
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7.7 Some Common Synchronizer Design Issues |
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133 | |
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7.7.1 Unsynchronized Paths |
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133 | |
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7.7.2 Moving Metastability Out of Sight |
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135 | |
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7.7.3 Multiple Synchronizer Flops |
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138 | |
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8 Networks and Interconnects |
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143 | |
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8.1 Communication on Chip |
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143 | |
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8.1.1 Comparison of Network Architectures |
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147 | |
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8.4 Differential Signalling |
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159 | |
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8.5.2 Transition Signalling |
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166 | |
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168 | |
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175 | |
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8.6 Parallel Serial Links |
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180 | |
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9 Pausible and Stoppable Clocks in GALS |
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183 | |
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9.1 GALS Clock Generators |
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184 | |
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188 | |
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Part III |
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197 | |
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199 | |
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199 | |
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200 | |
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11.3 Arbiter Applications, Resource Allocation Policies and Common Architectures |
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202 | |
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11.4 Signal Transition Graphs, Our Main Modelling Language |
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205 | |
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12 Simple Two-way Arbiters |
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209 | |
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12.1 Basic Concepts and Conventions |
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209 | |
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12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols |
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210 | |
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12.1.2 Four-phase or Return-to-zero (RTZ) Protocols |
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211 | |
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12.2 Simple Arbitration Between Two Asynchronous Requests |
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212 | |
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12.3 Sampling the Logic Level of an Asynchronous Request |
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217 | |
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12.4 Summary of Two-way Arbiters |
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222 | |
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225 | |
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13.1 Multi-way MUTEX Using a Mesh |
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226 | |
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13.2 Cascaded Tree Arbiters |
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227 | |
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14.5 Canonicai Structure of Priority Arbitcis |
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240 | |
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14.6 Static Priority Arbiter |
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241 | |
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14.7 Dynamic Priority Arbiter |
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246 | |
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253 | |
References |
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255 | |
Index |
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261 | |