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E-raamat: Synchronization and Arbitration in Digital Systems

(School of EECE)
  • Formaat: PDF+DRM
  • Ilmumisaeg: 28-Feb-2008
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9780470517130
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  • Formaat: PDF+DRM
  • Ilmumisaeg: 28-Feb-2008
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9780470517130

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Kinniment (engineering, U. of Newcastle) and his contributors provide both theory and practical design solutions to keep clocks and arbiters of shared resources operating reliably. Writing for electronic and computer engineers as well as senior undergraduates and graduate students, they take into consideration current developments in integrated circuit processing as they describe synchronization and arbitration, metastability and its measurement, circuits, noise and its effects, synchronizers in systems, networks and interconnects, clocks that can stop or pause, arbitration (including simple and multi-way arbiters) and priority arbiters. Kinniment includes a range of mathematical models, clear illustrations and samples and a very good section on the problem of choice in independently timed regions and the factors affecting the time taken to make choices in electronics. Annotation ©2008 Book News, Inc., Portland, OR (booknews.com)

Today’s networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first. Current developments in integrated circuit processing are leading to an increase in the numbers of independent digital processing elements in a single system. With this comes faster communications, more networks on chip, and the demand for more reliable, more complex, and higher performance synchronizers and arbiters. Written by one of the foremost researchers in this area of digital design, this authoritative text provides in-depth theory and practical design solutions for the reliable working of synchronization and arbitration hardware in digital systems.

The book provides methods for making real reliability measurements both on and off chip, evaluating some of the common difficulties and detailing circuit solutions at both circuit and system levels. Synchronization and Arbitration in Digital Systems also presents:

  • mathematical models used to estimate mean time between failures in digital systems;
  • a summary of serial and parallel communication techniques for on-chip data transmission;
  • explanations on how to design a wrapper for a locally synchronous cell, highlighting the issues associated with stoppable clocks;
  • an examination of various types of priority arbiters, using signal transition graphs to show the specification of different designs (from the simplest to more complex multi-way arbiters) including ways of solving problems encountered in a wide range of applications;
  • essential information on systems composed of independently timed regions, including a discussion on the problem of choice and the factors affecting the time taken to make choices in electronics.

With its logical approach to design methodology, this will prove an invaluable guide for electronic and computer engineers and researchers working on the design of digital electronic hardware. Postgraduates and senior undergraduate students studying digital systems design as part of their electronic engineering course will struggle to find a resource that better details the information given inside this book

Preface ix
List of Contributors xiii
Acknowledgements xv
1 Synchronization, Arbitration and Choice 1
1.1 Introduction
1
1.2 The Problem of Choice
2
1.3 Choice in Electronics
3
1.4 Arbitration
5
1.5 Continuous and Discrete Quantities
6
1.6 Timing
7
1.7 Book Structure
9
Part I 11
2 Modelling Metastability
13
2.1 The Synchronizer
14
2.2 Latch Model
21
2.3 Failure Rates
23
2.3.1 Event Histograms and MTBF
28
2.4 Latches and Flip-flops
32
2.5 Clock Back Edge
35
3 Circuits
39
3.1 Latches and Metastability Filters
39
3.2 Effects of Filtering
41
3.3 The Jamb Latch
42
3.3.1 Jamb Latch Flip-flop
45
3.4 Low Coupling Latch
47
3.5 The Q-flop
49
3.6 The MUTEX
50
3.7 Robust Synchronizer
52
3.8 The Tri-flop
55
4 Noise and its Effects
59
4.1 Noise
59
4.2 Effect of Noise on a Synchronizer
62
4.3 Malicious Inputs
63
4.3.1 Synchronous Systems
63
4.3.2 Asynchronous Systems
66
5 Metastability Measurements
69
5.1 Circuit Simulation
69
5.1.1 Time Step Control
70
5.1.2 Long-term τ
71
5.1.3 Using Bisection
73
5.2 Synchronizer Flip-flop Testing
75
5.3 Rising and Falling Edges
79
5.4 Delay-based Measurement
81
5.5 Deep Metastability
83
5.6 Back Edge Measurement
95
5.7 Measure and Select
97
5.7.1 Failure Measurement
97
5.7.2 Synchronizer Selection
98
6 Conclusions Part I
101
Part II 103
7 Synchronizers in Systems
105
7.1 Latency and Throughput
105
7.2 FIFO Synchronizer
108
7.3 Avoiding Synchronization
110
7.4 Predictive Synchronizers
113
7.5 Other Low-latency Synchronizers
115
7.5.1 Locally Delayed Latching (LDL)
115
7.5.2 Speculative Synchronization
118
7.6 Asynchronous Communication Mechanisms (ACM)
125
7.6.1 Slot Mechanisms
128
7.6.2 Three-slot Mechanism
128
7.6.3 Four-slot Mechanism
130
7.6.4 Hardware Design and Metastability
132
7.7 Some Common Synchronizer Design Issues
133
7.7.1 Unsynchronized Paths
133
7.7.2 Moving Metastability Out of Sight
135
7.7.3 Multiple Synchronizer Flops
138
8 Networks and Interconnects
143
8.1 Communication on Chip
143
8.1.1 Comparison of Network Architectures
147
8.2 Interconnect Links
150
8.3 Serial Links
155
8.3.1 Using One Line
155
8.3.2 Using Two Lines
157
8.4 Differential Signalling
159
8.5 Parallel Links
161
8.5.1 One Hot Codes
162
8.5.2 Transition Signalling
166
8.5.3 n of m Codes
167
8.5.4 Phase Encoding
168
8.5.5 Time Encoding
175
8.6 Parallel Serial Links
180
9 Pausible and Stoppable Clocks in GALS
183
9.1 GALS Clock Generators
184
9.2 Clock Tree Delays
188
9.3 A GALS Wrapper
190
10 Conclusions Part II
193
Part III 197
11 Arbitration
199
11.1 Introduction
199
11.2 Arbiter Definition
200
11.3 Arbiter Applications, Resource Allocation Policies and Common Architectures
202
11.4 Signal Transition Graphs, Our Main Modelling Language
205
12 Simple Two-way Arbiters
209
12.1 Basic Concepts and Conventions
209
12.1.1 Two-phase or Non-return-to-zero (NRZ) Protocols
210
12.1.2 Four-phase or Return-to-zero (RTZ) Protocols
211
12.2 Simple Arbitration Between Two Asynchronous Requests
212
12.3 Sampling the Logic Level of an Asynchronous Request
217
12.4 Summary of Two-way Arbiters
222
13 Multi-way Arbiters
225
13.1 Multi-way MUTEX Using a Mesh
226
13.2 Cascaded Tree Arbiters
227
13.3 Ring-based Arbiters
230
14 Priority Arbiters
235
14.1 Introduction
235
14.2 Priority Discipline
236
14.3 Daisy-chain Arbiter
238
14.4 Ordered Arbiter
239
14.5 Canonicai Structure of Priority Arbitcis
240
14.6 Static Priority Arbiter
241
14.7 Dynamic Priority Arbiter
246
15 Conclusions Part III
253
References 255
Index 261


David Kinniment is Professor Emeritus at the University of Newcastle, having been Professor of Electronics in the Department of Electrical, Electronic and Computer Engineering from 1979 until 1998. He currently works part time, mainly on asynchronous design and design methodology, in the Computer Science Department. He is very experienced in the measurement and characterization of synchronization and arbitration in digital systems, having been one of the leading researchers in the world in this area of digital design since the 1970s. He wrote the first paper to describe the measurement of mean time between failures (in other words, realiability) for a metastable device in 1972 and this year (2006) he won the best paper award at the ASYNC 2006 conference. Along with this, he has written a number of published journal articles on the topic, and has also collaborated with industry (most recently INTEL) to develop efficient digital hardware design methods, and ways of ensuring reliability in digital processors.