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E-raamat: System-on-a-Chip: Design and Test

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  • Formaat: 294 pages
  • Ilmumisaeg: 31-Jan-2000
  • Kirjastus: Artech House Publishers
  • ISBN-13: 9781580534710
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System-on-a-Chip: Design and TestSuurem pilt
  • Formaat: 294 pages
  • Ilmumisaeg: 31-Jan-2000
  • Kirjastus: Artech House Publishers
  • ISBN-13: 9781580534710
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An overview of the current state of a new technology Rajsuman, an electrical engineer now working as a manager in a research and development company, admits is changing too rapidly to capture in print very accurately. He avoids discussing general VLSI design and testing to focus only on aspects specific to system-on-a-chip. In the section on design he examines design methodology for logic, memory, and analog cores; design validation; and examples. Under testing he covers digital, analog, and mixed-signal logic cores; embedded memories; Iddq testing, and production testing. Annotation c. Book News, Inc., Portland, OR (booknews.com)
Preface xi
Acknowledgment xiii
Part I: Design 1(122)
Introduction
3(30)
Architecture of the Present-Day SoC
5(3)
Design Issues of SoC
8(6)
Hardware--Software Codesign
14(7)
Codesign Flow
15(3)
Codesign Tools
18(3)
Core Libraries, EDA Tools, and Web Pointers
21(12)
Core Libraries
21(2)
EDA Tools and Vendors
23(5)
Web Pointers
28(1)
References
29(4)
Design Methodology for Logic Cores
33(24)
SoC Design Flow
34(2)
General Guidelines for Design Reuse
36(7)
Synchronous Design
36(1)
Memory and Mixed-Signal Design
36(2)
On-Chip Buses
38(1)
Clock Distribution
39(1)
Clear/Set/Reset Signals
40(1)
Physical Design
40(2)
Deliverable Models
42(1)
Design Process for Soft and Firm Cores
43(4)
Design Flow
43(2)
Development Process for Soft/Firm Cores
45(1)
RTL Guidelines
46(1)
Soft/Firm Cores Productization
47(1)
Design Process for Hard Cores
47(4)
Unique Design Issues in Hard Cores
47(2)
Development Process for Hard Cores
49(2)
Sign-Off Checklist and Deliverables
51(2)
Sign-Off Checklist
51(1)
Soft Core Deliverables
52(1)
Hard Core Deliverables
53(1)
System Integration
53(4)
Designing With Hard Cores
53(1)
Designing With Soft Cores
54(1)
System Verification
54(1)
References
55(2)
Design Methodology for Memory and Analog Cores
57(28)
Why Large Embedded Memories
57(2)
Design Methodology for Embedded Memories
59(13)
Circuit Techniques
61(5)
Memory Compiler
66(4)
Simulation Models
70(2)
Specifications of Analog Circuits
72(7)
Analog-to-Digital Converter
72(3)
Digital-to-Analog Converter
75(3)
Phase-Locked Loops
78(1)
High-Speed Circuits
79(6)
Rambus ASIC Cell
79(1)
IEEE 1394 Serial Bus (Firewire) PHY Layer
80(1)
High-Speed I/O
81(1)
References
81(4)
Design Validation
85(20)
Core-Level Validation
86(7)
Core Validation Plan
86(2)
Testbenches
88(2)
Core-Level Timing Verification
90(3)
Core Interface Verification
93(2)
Protocol Verification
94(1)
Gate-Level Simulation
95(1)
SoC Design Validation
95(10)
Cosimulation
97(4)
Emulation
101(1)
Hardware Prototypes
101(2)
Reference
103(2)
Core and SoC Design Examples
105(18)
Microprocessor Cores
105(7)
V830R/AV Superscaler RISC Core
109(1)
Design of PowerPC 603e G2 Core
110(2)
Comments on Memory Core Generators
112(1)
Core Integration and On-Chip Bus
113(2)
Examples of SoC
115(8)
Media Processors
116(5)
Testability of Set-Top Box SoC
121(1)
References
122(1)
Part II: Test 123(134)
Testing of Digital Logic Cores
125(30)
SoC Test Issues
126(2)
Access, Control, and Isolation
128(1)
IEEE P1500 Effort
129(9)
Cores Without Boundary Scan
132(3)
Core Test Language
135(1)
Cores With Boundary Scan
135(3)
Core Test and IP Protection
138(4)
Test Methodology for Design Reuse
142(2)
Guidelines for Core Testability
142(1)
High-Level Test Synthesis
143(1)
Testing of Microprocessor Cores
144(11)
Built-in-Self-Test Method
144(3)
Example: Testability Features of ARM Processor Core
147(3)
Debug Support for Microprocessor Cores
150(2)
References
152(3)
Testing of Embedded Memories
155(26)
Memory Fault Models and Test Algorithms
156(5)
Fault Models
156(1)
Test Algorithms
157(3)
Effectiveness of Test Algorithms
160(1)
Modification With Multiple Data Background
161(1)
Modification for Multiport Memories
161(1)
Algorithm for Double-Buffered Memories
161(1)
Test Methods for Embedded Memories
161(10)
Testing Through ASIC Functional Test
163(1)
Test Application by Direct Access
164(1)
Test Application by Scan or Collar Register
164(1)
Memory Built-in Self-Test
164(5)
Testing by On-Chip Microprocessor
169(2)
Summary of Test Methods for Embedded Memories
171(1)
Memory Redundancy and Repair
171(4)
Hard Repair
171(4)
Soft Repair
175(1)
Error Detection and Correction Codes
175(1)
Production Testing of SoC With Large Embedded Memory
176(5)
References
177(4)
Testing of Analog and Mixed-Signal Cores
181(26)
Analog Parameters and Characterization
182(9)
Digital-to-Analog Converter
182(2)
Analog-to-Digital Converter
184(4)
Phase-Locked Loop
188(3)
Design-for-Test and Built-in Self-Test Methods for Analog Cores
191(9)
Fluence Technology's Analog BIST
192(1)
Logic Vision's Analog BIST
192(3)
Testing by On-Chip Microprocessor
195(2)
IEEE P1149.4
197(3)
Testing of Specific Analog Circuits
200(7)
Rambus ASIC Cell
200(1)
Testing of 1394 Serial Bus/Firewire
201(3)
References
204(3)
Iddq Testing
207(32)
Physical Defects
207(11)
Bridging (Shorts)
208(4)
Gate-Oxide Defects
212(1)
Open (Breaks)
213(2)
Effectiveness of Iddq Testing
215(3)
Iddq Testing Difficulties in SoC
218(6)
Design-for-Iddq-Testing
224(4)
Design Rules for Iddq Testing
228(2)
Iddq Test Vector Generation
230(9)
References
234(5)
Production Testing
239(12)
Production Test Flow
239(2)
At-Speed Testing
241(5)
RTD and Dead Cycles
241(2)
Fly-By
243(2)
Speed Binning
245(1)
Production Throughput and Material Handling
246(5)
Test Logistics
246(1)
Tester Setup
247(1)
Multi-DUT Testing
248(1)
References
249(2)
Summary and Conclusions
251(6)
Summary
251(3)
Future Scenarios
254(3)
Appendix: RTL Guidelines for Design Reuse 257(8)
A.1 Naming Convention
257(1)
A.2 General Coding Guidelines
258(2)
A.3 RTL Development for Synthesis
260(2)
A.4 RTL Checks
262(3)
About the Author 265(2)
Index 267
Rochit Rajsuman manages test research at Advantest America R & D Center in Santa Clara, California. He received his B.Tech. in Electrical Engineering from K.N. Institute of Technology, India, his M.S. in Electrical Engineering from the University of Oklahoma, and his Ph.D. in Electrical Engineering from Colorado State University. He is a senior member of the IEEE and a Golden Core member of the Computer Society.
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