Preface |
|
xi | |
About the Editors |
|
xiii | |
Contributor Biographies |
|
xv | |
|
|
1 | (26) |
|
|
|
|
Needs of a Complete and Efficient Design Environment |
|
|
1 | (11) |
|
|
3 | (4) |
|
Characteristics Expected from a Design Environment |
|
|
7 | (1) |
|
ESys.NET: A. NET Framework Based Design Environment |
|
|
8 | (3) |
|
Our Design, Simulation and Verification Flows |
|
|
11 | (1) |
|
Design Flow with ESys.NET |
|
|
12 | (5) |
|
Modeling and Specification |
|
|
13 | (1) |
|
|
13 | (3) |
|
Analysis of the Design Flow |
|
|
16 | (1) |
|
Simulation Flow with ESys.NET |
|
|
17 | (3) |
|
Building the Simulation Model |
|
|
17 | (1) |
|
Separation of Concerns between Models and Simulation |
|
|
17 | (1) |
|
Towards a Multi-Level Simulation Model |
|
|
18 | (2) |
|
Observer-Based Verification Flow with ESys.NET |
|
|
20 | (3) |
|
Overview of the Observer-Based Verification Flow |
|
|
20 | (1) |
|
Building and Binding the Verification Engine to the Simulation Model |
|
|
21 | (1) |
|
Comparison with the Same Verification Flow in SystemC |
|
|
22 | (1) |
|
Towards a Powerful Verification Flow |
|
|
23 | (1) |
|
Conclusion and Book Organization |
|
|
23 | (4) |
|
I Modeling and Specification |
|
|
27 | (88) |
|
High-Level Requirments Engineering for Electronic System-Level Design |
|
|
29 | (26) |
|
|
|
29 | (2) |
|
|
31 | (4) |
|
|
31 | (2) |
|
Software Engineering Approaches |
|
|
33 | (2) |
|
|
35 | (8) |
|
|
35 | (3) |
|
Linguistic Pre-Processing |
|
|
38 | (2) |
|
|
40 | (2) |
|
Elicitation of Missing Functionalities |
|
|
42 | (1) |
|
|
43 | (6) |
|
Automatic Door Controller |
|
|
43 | (3) |
|
|
46 | (2) |
|
|
48 | (1) |
|
Linking to a UML-Based Methodology |
|
|
49 | (3) |
|
|
50 | (1) |
|
|
51 | (1) |
|
|
52 | (3) |
|
The Semantic Web Applied to IP-Based Design: a Discussion on IP-XACT |
|
|
55 | (34) |
|
|
|
|
|
55 | (2) |
|
Models of Architecture and XML |
|
|
57 | (4) |
|
|
57 | (2) |
|
|
59 | (1) |
|
|
59 | (2) |
|
|
61 | (2) |
|
|
61 | (1) |
|
Tight Generator Interface (TGI) |
|
|
62 | (1) |
|
Semantic Consistency Rules (SCR) |
|
|
63 | (1) |
|
|
63 | (9) |
|
Resource Description Framework |
|
|
64 | (1) |
|
|
65 | (1) |
|
Web Ontology Language (OWL) |
|
|
66 | (2) |
|
|
68 | (1) |
|
Tool for the Semantic Web: Editors and Jena |
|
|
69 | (1) |
|
|
70 | (2) |
|
|
72 | (4) |
|
|
72 | (1) |
|
|
73 | (1) |
|
|
74 | (1) |
|
|
75 | (1) |
|
Advantages of the Semantic Web |
|
|
76 | (3) |
|
Richer Semantic Expressivity |
|
|
76 | (1) |
|
Separation between Semantics and Encoding |
|
|
77 | (1) |
|
|
77 | (1) |
|
Simpler Data Manipulation |
|
|
78 | (1) |
|
|
79 | (7) |
|
Advantages Applied to Version Management (SPIRIT 1.2 to SPIRIT 1.4) |
|
|
80 | (1) |
|
Advantages Applied to Modeling |
|
|
80 | (2) |
|
|
82 | (1) |
|
Implications for SPIRIT Semantic Constraint Rules (SCRs) |
|
|
83 | (2) |
|
|
85 | (1) |
|
|
86 | (2) |
|
|
88 | (1) |
|
|
88 | (1) |
|
Translating Design Pattern Concepts to Hardware Concepts |
|
|
89 | (26) |
|
|
|
|
|
89 | (3) |
|
Object-Oriented Translations |
|
|
92 | (6) |
|
Translation of Classes and Their Members |
|
|
92 | (1) |
|
Translation of Object Encapsulation |
|
|
92 | (1) |
|
Translation of Object Instantiation |
|
|
93 | (1) |
|
Translation of Object Method Calls |
|
|
94 | (1) |
|
Translation of Polymorphism |
|
|
94 | (3) |
|
Translation of Inheritance and Casting Operations |
|
|
97 | (1) |
|
Constraint and Assumptions for Design Pattern Synthesis |
|
|
98 | (2) |
|
Constraint: Dynamism of the Hardware |
|
|
98 | (1) |
|
Assumption: Compiled Once |
|
|
98 | (1) |
|
Assumption: Limited Number of Objects |
|
|
99 | (1) |
|
Assumption: Pattern Automatic Recognition Problem |
|
|
99 | (1) |
|
Translation Cost versus Performance |
|
|
100 | (1) |
|
|
100 | (3) |
|
|
101 | (1) |
|
|
101 | (2) |
|
|
103 | (1) |
|
Operational Description of Design Patterns |
|
|
103 | (8) |
|
|
104 | (1) |
|
|
104 | (2) |
|
|
106 | (3) |
|
|
109 | (2) |
|
|
111 | (1) |
|
Related Work & Background |
|
|
111 | (2) |
|
Object Oriented Synthesis & Patterns in Hardware |
|
|
111 | (2) |
|
|
113 | (1) |
|
|
113 | (2) |
|
II Simulation and Validation |
|
|
115 | (124) |
|
Using Transaction-Based Models for System Design and Simulation |
|
|
117 | (38) |
|
|
|
|
|
|
117 | (2) |
|
|
119 | (3) |
|
|
122 | (12) |
|
|
123 | (4) |
|
STM Implementation Techniques |
|
|
127 | (2) |
|
STM Implementation Examples |
|
|
129 | (5) |
|
STM Implementation Using.NET |
|
|
134 | (16) |
|
|
135 | (4) |
|
NSTM Transactional Memory |
|
|
139 | (2) |
|
|
141 | (4) |
|
|
145 | (5) |
|
|
150 | (3) |
|
Conclusion and Future Work |
|
|
153 | (2) |
|
Simulation at Cycle Accurate and Transaction Accurate Levels |
|
|
155 | (22) |
|
|
|
|
155 | (1) |
|
Short Presentation of the Cycle Accurate and Transaction Accurate Abstraction Levels |
|
|
156 | (1) |
|
Cycle Accurate Simulation |
|
|
157 | (10) |
|
|
157 | (1) |
|
|
158 | (1) |
|
|
158 | (4) |
|
|
162 | (5) |
|
Transaction Accurate Simulation |
|
|
167 | (8) |
|
|
167 | (2) |
|
|
169 | (2) |
|
Native Simulation for MPSoC |
|
|
171 | (4) |
|
|
175 | (2) |
|
An Introduction to Cosimulation and Compliation Methods |
|
|
177 | (26) |
|
|
|
|
|
177 | (3) |
|
|
180 | (11) |
|
Preliminaries: Managed and Unmanaged Code |
|
|
181 | (1) |
|
|
182 | (1) |
|
|
182 | (1) |
|
|
182 | (1) |
|
|
183 | (1) |
|
|
184 | (1) |
|
|
185 | (2) |
|
|
187 | (2) |
|
Comparison of Cosimulation Implementations |
|
|
189 | (2) |
|
|
191 | (11) |
|
Common Intermediate Format |
|
|
191 | (2) |
|
|
193 | (6) |
|
|
199 | (1) |
|
|
199 | (1) |
|
|
200 | (2) |
|
|
202 | (1) |
|
Timing Specification in Transaction Level Models |
|
|
203 | (36) |
|
|
|
|
|
203 | (1) |
|
|
204 | (3) |
|
|
207 | (14) |
|
Linear Constraint Systems |
|
|
208 | (1) |
|
|
209 | (2) |
|
|
211 | (4) |
|
Min-Max Constraint Systems |
|
|
215 | (1) |
|
Min-Max-Linear Constraint Systems |
|
|
216 | (1) |
|
Assume-Commit Constraint Systems |
|
|
217 | (4) |
|
|
221 | (1) |
|
Min-Max Constraint Linearization Algorithm |
|
|
221 | (9) |
|
Min-Max Constraint Linearization |
|
|
221 | (4) |
|
|
225 | (2) |
|
|
227 | (3) |
|
|
230 | (8) |
|
Timing Modeling at CP+T Level |
|
|
231 | (1) |
|
Communication Exploration at PV and PV+T Levels |
|
|
232 | (6) |
|
|
238 | (1) |
|
III Practical Use of ESys.NET |
|
|
239 | (42) |
|
|
241 | (40) |
|
|
|
|
241 | (1) |
|
|
242 | (18) |
|
|
242 | (4) |
|
|
246 | (7) |
|
|
253 | (1) |
|
|
253 | (7) |
|
|
260 | (10) |
|
Simulator Semantics and Construction |
|
|
260 | (1) |
|
|
261 | (9) |
|
|
270 | (9) |
|
|
270 | (1) |
|
Case-Study Model: The AHB-Lite Bus |
|
|
270 | (2) |
|
How to Specify Properties |
|
|
272 | (3) |
|
Verifying Temporal Properties during Simulation |
|
|
275 | (2) |
|
|
277 | (1) |
|
|
278 | (1) |
|
|
279 | (2) |
References |
|
281 | (16) |
Index |
|
297 | |