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E-raamat: System Level Design with .Net Technology

Edited by (TIMA Lab, France), Edited by (Universite de Montreal, Canada)
  • Formaat: 320 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781439812129
  • Formaat - PDF+DRM
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  • Formaat: 320 pages
  • Ilmumisaeg: 03-Oct-2018
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781439812129

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The first book to harness the power of .NET for system design, System Level Design with .NET Technology constitutes a software-based approach to design modeling verification and simulation. World class developers, who have been at the forefront of system design for decades, explain how to tap into the power of this dynamic programming environment for more effective and efficient management of metadataand introspection and interoperability between tools.

Using readily available technology, the text details how to capture constraints and requirements at high levels and describes how to percolate them during the refinement process. Departing from proprietary environments built around System Verilog and VHDL, this cutting-edge reference includes an open source environment (ESys.NET) that readers can use to experiment with new ideas, algorithms, and design methods; and to expand the capabilities of their current tools. It also covers:











Modeling and simulationincluding requirements specification, IP reuse, and applications of design patterns to hardware/software systems





Simulation and validationincluding transaction-based models, accurate simulation at cycle and transaction levels, cosimulation and acceleration technique, as well as timing specification and validation





Practical use of the ESys.NET environment

Worked examples, end of chapter references, and the ESys.NET implementation test bed make this the ideal resource for system engineers and students looking to maximize their embedded system designs.
Preface xi
About the Editors xiii
Contributor Biographies xv
Introduction
1(26)
Frederic Rousseau
James Lapalme
El Mostapha Aboulhamid
Needs of a Complete and Efficient Design Environment
1(11)
The.NET Framework
3(4)
Characteristics Expected from a Design Environment
7(1)
ESys.NET: A. NET Framework Based Design Environment
8(3)
Our Design, Simulation and Verification Flows
11(1)
Design Flow with ESys.NET
12(5)
Modeling and Specification
13(1)
Our System Design Flow
13(3)
Analysis of the Design Flow
16(1)
Simulation Flow with ESys.NET
17(3)
Building the Simulation Model
17(1)
Separation of Concerns between Models and Simulation
17(1)
Towards a Multi-Level Simulation Model
18(2)
Observer-Based Verification Flow with ESys.NET
20(3)
Overview of the Observer-Based Verification Flow
20(1)
Building and Binding the Verification Engine to the Simulation Model
21(1)
Comparison with the Same Verification Flow in SystemC
22(1)
Towards a Powerful Verification Flow
23(1)
Conclusion and Book Organization
23(4)
I Modeling and Specification
27(88)
High-Level Requirments Engineering for Electronic System-Level Design
29(26)
Nicolas Gorse
Introduction
29(2)
Background
31(4)
Framework
31(2)
Software Engineering Approaches
33(2)
Proposed Solution
35(8)
Formalism
35(3)
Linguistic Pre-Processing
38(2)
Consistency Validation
40(2)
Elicitation of Missing Functionalities
42(1)
Experimental Results
43(6)
Automatic Door Controller
43(3)
Industrial Router
46(2)
RapidIO
48(1)
Linking to a UML-Based Methodology
49(3)
Integrated Methodology
50(1)
Case Study
51(1)
Conclusion
52(3)
The Semantic Web Applied to IP-Based Design: a Discussion on IP-XACT
55(34)
James Lapalme
El Mostapha Aboulhamid
Gabriela Nicolescu
Introduction
55(2)
Models of Architecture and XML
57(4)
GSRC and MoML
57(2)
Colif and Middle-ML
59(1)
Premadona
59(2)
SPIRIT
61(2)
IP-XACT Metadata Format
61(1)
Tight Generator Interface (TGI)
62(1)
Semantic Consistency Rules (SCR)
63(1)
The Semantic Web
63(9)
Resource Description Framework
64(1)
RDF Schema
65(1)
Web Ontology Language (OWL)
66(2)
SPARQL
68(1)
Tool for the Semantic Web: Editors and Jena
69(1)
SWRL and Jena rules
70(2)
XML and its Shortcomings
72(4)
Multiple Grammars
72(1)
Documentation-Centric
73(1)
Biased Grammar Model
74(1)
Limited Metadata
75(1)
Advantages of the Semantic Web
76(3)
Richer Semantic Expressivity
76(1)
Separation between Semantics and Encoding
77(1)
Federated Data Model
77(1)
Simpler Data Manipulation
78(1)
Case Study - SPIRIT
79(7)
Advantages Applied to Version Management (SPIRIT 1.2 to SPIRIT 1.4)
80(1)
Advantages Applied to Modeling
80(2)
Impact on TGI
82(1)
Implications for SPIRIT Semantic Constraint Rules (SCRs)
83(2)
Dependency XPath
85(1)
Cost of Adoption
86(2)
Future Research
88(1)
Conclusion
88(1)
Translating Design Pattern Concepts to Hardware Concepts
89(26)
Luc Charest
Yann-Gael Gueheneuc
Yousra Tagmouti
Introduction
89(3)
Object-Oriented Translations
92(6)
Translation of Classes and Their Members
92(1)
Translation of Object Encapsulation
92(1)
Translation of Object Instantiation
93(1)
Translation of Object Method Calls
94(1)
Translation of Polymorphism
94(3)
Translation of Inheritance and Casting Operations
97(1)
Constraint and Assumptions for Design Pattern Synthesis
98(2)
Constraint: Dynamism of the Hardware
98(1)
Assumption: Compiled Once
98(1)
Assumption: Limited Number of Objects
99(1)
Assumption: Pattern Automatic Recognition Problem
99(1)
Translation Cost versus Performance
100(1)
Design Pattern Mappings
100(3)
Creational Patterns
101(1)
Structural Patterns
101(2)
Behavioral Patterns
103(1)
Operational Description of Design Patterns
103(8)
PADL in a Nutshell
104(1)
PADL in Details
104(2)
PADL by Examples
106(3)
MIP
109(2)
ESys.NET Code Generation
111(1)
Related Work & Background
111(2)
Object Oriented Synthesis & Patterns in Hardware
111(2)
Original Patterns
113(1)
Conclusion
113(2)
II Simulation and Validation
115(124)
Using Transaction-Based Models for System Design and Simulation
117(38)
Amine Anane
El Mostapha Aboulhamid
Julie Vachon
Yvon Savaria
Introduction
117(2)
Motivations
119(3)
Transaction Model
122(12)
STM Concurrent Execution
123(4)
STM Implementation Techniques
127(2)
STM Implementation Examples
129(5)
STM Implementation Using.NET
134(16)
SXM Transactional Memory
135(4)
NSTM Transactional Memory
139(2)
PostSharp
141(4)
STM Framework
145(5)
Experimental Results
150(3)
Conclusion and Future Work
153(2)
Simulation at Cycle Accurate and Transaction Accurate Levels
155(22)
Frederic Petrot
Patrice Gerin
Introduction
155(1)
Short Presentation of the Cycle Accurate and Transaction Accurate Abstraction Levels
156(1)
Cycle Accurate Simulation
157(10)
General Description
157(1)
System Properties
158(1)
Formal Model
158(4)
Simulator Implementation
162(5)
Transaction Accurate Simulation
167(8)
General Description
167(2)
Basic Concepts
169(2)
Native Simulation for MPSoC
171(4)
Summary and Conclusions
175(2)
An Introduction to Cosimulation and Compliation Methods
177(26)
Mathieu Dubois
Frederic Rousseau
El Mostapha Aboulhamid
Introduction
177(3)
Cosimulation
180(11)
Preliminaries: Managed and Unmanaged Code
181(1)
Same Binary File
182(1)
Shared Memory
182(1)
TCP/IP
182(1)
COM
183(1)
Static Function
184(1)
Pinvoke
185(2)
Managed Wrapper
187(2)
Comparison of Cosimulation Implementations
189(2)
Compiler Framework
191(11)
Common Intermediate Format
191(2)
Internal Data Structures
193(6)
Code Generation
199(1)
Compiled RTL
199(1)
Compiled TLM
200(2)
Conclusion
202(1)
Timing Specification in Transaction Level Models
203(36)
Alena Tsikhanovich
El Mostapha Aboulhamid
Guy Bois
Summary
203(1)
Expressing Timing
204(3)
Timing Analysis
207(14)
Linear Constraint Systems
208(1)
Max Constraint Systems
209(2)
Max-Linear Systems
211(4)
Min-Max Constraint Systems
215(1)
Min-Max-Linear Constraint Systems
216(1)
Assume-Commit Constraint Systems
217(4)
Discussion
221(1)
Min-Max Constraint Linearization Algorithm
221(9)
Min-Max Constraint Linearization
221(4)
Algorithm Optimization
225(2)
Experimentations
227(3)
Timing in TLM
230(8)
Timing Modeling at CP+T Level
231(1)
Communication Exploration at PV and PV+T Levels
232(6)
Conclusion
238(1)
III Practical Use of ESys.NET
239(42)
ESys.NET Environment
241(40)
James Lapalme
Michel Metzger
Introduction
241(1)
Modeling
242(18)
My First Model
242(4)
Modeling Concepts
246(7)
Process Method
253(1)
Signals
253(7)
Simulation
260(10)
Simulator Semantics and Construction
260(1)
Semantics
261(9)
Verification
270(9)
Overview
270(1)
Case-Study Model: The AHB-Lite Bus
270(2)
How to Specify Properties
272(3)
Verifying Temporal Properties during Simulation
275(2)
Linking Different Tools
277(1)
Observing Results
278(1)
Conclusion
279(2)
References 281(16)
Index 297
El Mostapha Aboulhamid, Frederic Rousseau