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E-raamat: Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables

(Université Catholique de Louvain, Belgium), (Stanford University, California)
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 12-Oct-2017
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9781108135474
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  • Formaat: EPUB+DRM
  • Ilmumisaeg: 12-Oct-2017
  • Kirjastus: Cambridge University Press
  • Keel: eng
  • ISBN-13: 9781108135474

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Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

This hands-on guide contains a fresh approach to efficient and insight-driven integrated circuit design in nanoscale-CMOS. With downloadable MATLAB code and over forty detailed worked examples, this is essential reading for professional engineers, researchers, and graduate students in analog circuit design.

Arvustused

'Analog design generates insight, but requires expertise. To build up such expertise, analytic models are used to create design procedures. Indeed, analytic models easily allow device sizing from specifications. They lack accuracy, however. The models of present-day nanometer MOS transistors have become rather complicated. On the other hand SPICE simulations do provide the required accuracy but don't generate as much insight. The use of SPICE-generated lookup tables, as described in this book, provides an excellent compromise. The accuracy is derived from SPICE, and the design procedure itself is made through MATLAB employing parameters like gm/ID. As a result, a considerable amount of intuition can be built up. Such design procedure is highly recommended to whoever wants to gain insight by doing analog design, without losing the accuracy of real SPICE simulations.' Willy Sansen, Katholieke Universiteit Leuven, Belgium 'With the advent of sub-micron MOS transistors more than two decades ago, traditional design based on the square-law model is no longer adequate. Alternatives such as 'tweaking' with SPICE or relying on more sophisticated device models do not provide the circuit insight necessary for optimized design or are too mathematically complex. The design methodology presented in this book overcomes these shortcomings. A focus on fundamental design parameters - dynamic range, bandwidth, power dissipation - naturally leads to optimized solutions, while relying on transistor data extracted with the simulator ensures agreement between design and verification. Comprehensive design examples of common blocks such as OTAs show how to readily apply these concepts in practice. This book fixes what has been broken with analog design for more than twenty years. I recommend it to experts and novices alike.' Bernhard Boser, University of California, Berkeley 'The authors present a clever solution to capture the precision of the best MOSFET models, current or future, in a comprehensive and efficient design flow compatible with nanometric CMOS processes. In this book, you will also enjoy a wealth of invaluable information to deepen your analog design skills.' Yves Leduc, Polytech Nice-Sophia, France 'Jespers and Murmann have taken a hard look at a notoriously thorny problem and produced a work of great clarity and practical value. This book will be a tremendous help to analog designers of all experience levels.' Joel Dawson, Massachusetts Institute of Technology

Muu info

Discover a fresh approach to efficient and insight-driven analog integrated circuit design with this hands-on guide.
Symbols and Acronyms xii
1 Introduction
1(20)
1.1 Motivation
1(4)
1.2 The Analog Circuit Sizing Problem and the Proposed Approach
5(12)
1.2.1 Square-Law Perspective
6(3)
1.2.2 Capturing the Tradeoffs Using Lookup Tables
9(2)
1.2.3 Generalization
11(4)
1.2.4 VGS-agnostic design
15(1)
1.2.5 Design in Weak Inversion
15(2)
1.3 Content Overview
17(1)
1.4 Prerequisites
18(1)
1.5 Notation
18(1)
1.6 References
19(2)
2 Basic Transistor Modeling
21(41)
2.1 The Charge Sheet Model (CSM)
21(7)
2.1.1 The CSM Drain Current Equation
21(3)
Example 2.1 Surface Potential Calculation
24(1)
2.1.2 The Dependence of the Drain Current on the Drain Voltage
25(2)
2.1.3 The Transconductance Efficiency gm/ID
27(1)
2.2 The Basic EKV Model
28(11)
2.2.1 The Basic EKV Equations
28(4)
2.2.2 The Basic EKV Model for a Grounded-Source MOS Transistor
32(1)
2.2.3 Strong and Weak Inversion Approximations of the EKV Model
33(1)
2.2.4 Basic EKV Model Expressions for gm and gm/ID
34(2)
2.2.5 EKV Parameter Extraction
36(1)
Example 2.2 EKV Parameter Extraction for the CSM Device
37(2)
2.3 Real Transistors
39(21)
2.3.1 Real Drain Current Characteristics ID(VGS) and gm/ID
39(2)
Example 2.3 EKV Parameter Extraction for Real Transistors
41(4)
2.3.2 The Drain Saturation Voltage VDsat of Real Transistors
45(2)
2.3.3 Impact of Bias Conditions on EKV Parameters
47(2)
2.3.4 The Drain Current Characteristic ID(VDS)
49(2)
2.3.5 The Output Conductance gds
51(2)
2.3.6 The gds/ID Ratio
53(1)
2.3.7 The Intrinsic Gain
54(1)
2.3.8 MOSFET Capacitances and the Transit Frequency ƒT
55(5)
2.4 Summary
60(1)
2.5 References
61(1)
3 Basic Sizing Using the gm/ID Methodology
62(30)
3.1 Sizing an Intrinsic Gain Stage (IGS)
62(30)
3.1.1 Circuit Analysis
62(3)
3.1.2 Sizing Considerations
65(1)
3.1.3 Sizing for Given L and gm/ID
66(1)
Example 3.1 A Basic Sizing Example
67(3)
3.1.4 Basic Tradeoff Exploration
70(1)
Example 3.2 Sizing at Constant gm/ID
71(2)
Example 3.3 Sizing at Constant ƒT
73(4)
Example 3.4 Sizing at Constant |Av0|
77(2)
3.1.5 Sizing in Weak Inversion
79(3)
Example 3.5 Sizing in Weak Inversion Given a Width Constraint
82(1)
3.1.6 Sizing Using the Drain Current Density
83(4)
Example 3.6 Sizing Using Contours in the JD and L Plane
87(3)
3.1.7 Inclusion of Extrinsic Capacitances
90(2)
Example 3.7 Iterative Sizing to Account for Self-Loading
92(22)
3.2 Practical Common-Source Stages
93(9)
3.2.1 Active Load
94(1)
Example 3.8 Sizing a CS Stage with Active Load
95(3)
Example 3.9 Large-Signal Characteristic of a CS Stage with Active Load
98(1)
3.2.2 Resistive Load
99(2)
Example 3.10 Sizing a CS Stage with Resistive Load
101(1)
3.3 Differential Amplifier Stages
102(11)
Example 3.11 Sizing a Differential Pair with Ideal Current Source Loads
105(3)
Example 3.12 Sizing a Differential Amplifier with Current-Mirror Load
108(3)
Example 3.13 Sizing a Differential Amplifier with Resistive Input Driver and Resistive Loads
111(2)
3.4 Summary
113(1)
3.5 References
113(1)
4 Noise, Distortion and Mismatch
114(51)
4.1 Electronic Noise
114(12)
4.1.1 Thermal Noise Modeling
114(3)
4.1.2 Tradeoff between Thermal Noise, GBW and Supply Current
117(1)
Example 4.1 Sizing of a Low-Noise IGS
118(1)
4.1.3 Thermal Noise from Active Loads
119(1)
Example 4.2 Choosing gm/ID of a p-Channel Load for Maximum Dynamic Range
120(1)
4.1.4 Flicker Noise (1/ƒ Noise)
121(4)
Example 4.3 Estimation of the Flicker Noise Corner Frequency
125(1)
4.2 Nonlinear Distortion
126(24)
4.2.1 Nonlinearity of the MOS Transconductance
126(5)
4.2.2 Nonlinearity of the MOS Differential Pair
131(5)
Example 4.4 Sizing a Differential Amplifier Based on Distortion Specs
136(3)
4.2.3 Inclusion of the Output Conductance
139(7)
Example 4.5 Sizing of a Resistively Loaded CS Stage with Low HD2
146(3)
Example 4.6 Sizing of a Resistively Loaded CS Stage with Low FfD2 and VDD = 1.2 V
149(1)
4.3 Random Mismatch
150(12)
4.3.1 Modeling of Random Mismatch
151(2)
4.3.2 Effect of Mismatch in a Current Mirror
153(1)
Example 4.7 Random Mismatch Estimation in a Current Mirror
154(5)
4.3.3 Effect of Mismatch in a Differential Amplifier
159(3)
Example 4.8 Offset Drift Estimation
162(1)
4.4 Summary
162(1)
4.5 References
163(2)
5 Practical Circuit Examples I
165(61)
5.1 Constant Transconductance Bias Circuit
165(6)
Example 5.1 Sizing of a Constant Transconductance Bias Circuit
168(3)
5.2 High-Swing Cascoded Current Mirror
171(6)
5.2.1 Sizing the Current Mirror Devices
174(1)
5.2.2 Sizing the Cascode Bias Circuit
175(2)
5.3 Low-Dropout Voltage Regulator
177(12)
5.3.1 Low-Frequency Analysis
180(1)
Example 5.2 Basic Sizing of an LDO
181(3)
5.3.2 High-Frequency Analysis
184(3)
Example 5.3 Sizing the LDO's Load Capacitance
187(2)
5.4 RF Low-Noise Amplifier
189(11)
5.4.1 Sizing for Low-Noise Figure
190(2)
Example 5.4 Sizing the LNA for a Given Noise Figure
192(4)
5.4.2 Sizing for Low-Noise Figure and Low Distortion
196(1)
Example 5.5 Sizing the LNA for Minimum HD2
197(3)
5.5 Charge Amplifier
200(14)
5.5.1 Circuit Analysis
201(3)
5.5.2 Optimization Assuming Constant Transit Frequency
204(1)
5.5.3 Optimization Assuming Constant Drain Current
205(1)
Example 5.6 Charge Amplifier Optimization (Constant ID)
205(2)
5.5.4 Optimization Assuming Constant Noise and Bandwidth
207(2)
Example 5.7 Charge Amplifier Optimization (Constant Noise and Bandwidth)
209(1)
Example 5.8 Charge Amplifier Sizing
210(3)
Example 5.9 Charge Amplifier Re-sizing for Smaller Area
213(1)
5.6 Designing for Process Corners
214(10)
5.6.1 Biasing Considerations
214(2)
5.6.2 Technology Evaluation over Process and Temperature
216(4)
Example 5.10 Constant Transconductance Bias Circuit Performance across Process Corners
220(1)
5.6.3 Possible Design Flows
221(1)
Example 5.11 Design of a Charge Amplifier with Corner Awareness
222(2)
5.7 Summary
224(1)
5.8 References
225(1)
6 Practical Circuit Examples II
226(96)
6.1 Basic OTA for Switched-Capacitor Circuits
226(23)
6.1.1 Small-Signal Circuit Analysis
226(5)
6.1.2 Optimization Assuming Constant Noise and Bandwidth
231(2)
Example 6.1 Optimization of the Basic OTA
233(4)
Example 6.2 Sizing of the Basic OTA
237(5)
6.1.3 Optimization in Presence of Slewing
242(3)
Example 6.3 Sizing of the Basic OTA Circuit in Presence of Slewing
245(4)
6.2 Folded-Cascode OTA for Switched-Capacitor Circuits
249(18)
6.2.1 Design Equations
249(6)
6.2.2 Optimization Procedure
255(1)
Example 6.4 Sizing of the Folded-Cascode Output Branch
255(3)
Example 6.5 Optimization of the Folded-Cascode OTA
258(4)
Example 6.6 Sizing the Folded-Cascode OTA
262(4)
6.2.3 Optimization in Presence of Slewing
266(1)
6.3 Two-Stage OTA for Switched-Capacitor Circuits
267(16)
6.3.1 Design Equations
268(2)
6.3.2 Optimization Procedure
270(2)
Example 6.7 Optimization of the Two-Stage OTA
272(5)
Example 6.8 Sizing the Two-Stage OTA
277(4)
6.3.3 Optimization in Presence of Slewing
281(2)
6.4 Simplified Design Flows
283(2)
6.4.1 Folded-Cascode OTA
284(1)
6.4.2 Two-Stage OTA
284(1)
6.5 Sizing Switches
285(4)
Example 6.9 Sizing a Transmission Gate Switch
288(1)
6.6 Summary
289(1)
6.7 References
290(2)
Appendix 1 The EKV Parameter Extraction Algorithm
292(11)
A.1.1 Review of Equations
292(1)
A.1.2 Parameter Extraction Algorithm
292(2)
A.1.3 Matlab Function XTRACT.m
294(1)
A.1.4 Parameter Extraction Example
294(3)
A.1.5 Matlab Function XTRACT2.m
297(2)
A.1.6 Corner Parameter Extraction
299(3)
A.1.7 Conclusion
302(1)
A.1.8 References
302(1)
Appendix 2 Lookup Table Generation and Usage
303(12)
A.2.1 Lookup Table Generation
303(2)
A.2.1.1 Configuration File
305(2)
A.2.1.2 Generating Lookup Tables for a New Technology
307(1)
A.2.2 Matlab Function lookup.m
307(2)
A.2.3 Matlab Function lookupVGS.m
309(1)
A.2.4 Lookup of Ratios with Non-monotonic Vectors
310(3)
A.2.5 LookupVGS with Non-monotonic gm/ID Vector
313(1)
A.2.6 Passing Design Variables to the Simulator
313(1)
A.2.7 References
314(1)
Appendix 3 Layout Dependence
315(7)
A.3.1 Introduction to Layout Dependent Effects (LDE)
315(1)
A.3.2 Transistor Finger Partitioning
316(1)
A.3.3 Width Dependence of Parameter Ratios
317(4)
A.3.4 References
321(1)
Index 322
Paul G. A. Jespers is a Professor Emeritus of the Université Catholique de Louvain, Belgium and a Life Fellow of the Institute of Electrical and Electronics Engineers (IEEE). Boris Murmann is a Professor of Electrical Engineering at Stanford University, California, and a Fellow of the Institute of Electrical and Electronics Engineers (IEEE).