Symbols and Acronyms |
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1 | (20) |
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1 | (4) |
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1.2 The Analog Circuit Sizing Problem and the Proposed Approach |
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5 | (12) |
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1.2.1 Square-Law Perspective |
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6 | (3) |
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1.2.2 Capturing the Tradeoffs Using Lookup Tables |
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9 | (2) |
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11 | (4) |
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1.2.4 VGS-agnostic design |
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15 | (1) |
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1.2.5 Design in Weak Inversion |
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15 | (2) |
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17 | (1) |
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18 | (1) |
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18 | (1) |
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19 | (2) |
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2 Basic Transistor Modeling |
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21 | (41) |
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2.1 The Charge Sheet Model (CSM) |
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21 | (7) |
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2.1.1 The CSM Drain Current Equation |
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21 | (3) |
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Example 2.1 Surface Potential Calculation |
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24 | (1) |
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2.1.2 The Dependence of the Drain Current on the Drain Voltage |
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25 | (2) |
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2.1.3 The Transconductance Efficiency gm/ID |
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27 | (1) |
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28 | (11) |
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2.2.1 The Basic EKV Equations |
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28 | (4) |
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2.2.2 The Basic EKV Model for a Grounded-Source MOS Transistor |
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32 | (1) |
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2.2.3 Strong and Weak Inversion Approximations of the EKV Model |
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33 | (1) |
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2.2.4 Basic EKV Model Expressions for gm and gm/ID |
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34 | (2) |
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2.2.5 EKV Parameter Extraction |
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36 | (1) |
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Example 2.2 EKV Parameter Extraction for the CSM Device |
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37 | (2) |
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39 | (21) |
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2.3.1 Real Drain Current Characteristics ID(VGS) and gm/ID |
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39 | (2) |
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Example 2.3 EKV Parameter Extraction for Real Transistors |
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41 | (4) |
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2.3.2 The Drain Saturation Voltage VDsat of Real Transistors |
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45 | (2) |
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2.3.3 Impact of Bias Conditions on EKV Parameters |
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47 | (2) |
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2.3.4 The Drain Current Characteristic ID(VDS) |
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49 | (2) |
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2.3.5 The Output Conductance gds |
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51 | (2) |
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53 | (1) |
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54 | (1) |
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2.3.8 MOSFET Capacitances and the Transit Frequency ƒT |
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55 | (5) |
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60 | (1) |
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61 | (1) |
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3 Basic Sizing Using the gm/ID Methodology |
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62 | (30) |
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3.1 Sizing an Intrinsic Gain Stage (IGS) |
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62 | (30) |
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62 | (3) |
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3.1.2 Sizing Considerations |
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65 | (1) |
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3.1.3 Sizing for Given L and gm/ID |
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66 | (1) |
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Example 3.1 A Basic Sizing Example |
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67 | (3) |
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3.1.4 Basic Tradeoff Exploration |
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70 | (1) |
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Example 3.2 Sizing at Constant gm/ID |
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71 | (2) |
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Example 3.3 Sizing at Constant ƒT |
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73 | (4) |
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Example 3.4 Sizing at Constant |Av0| |
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77 | (2) |
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3.1.5 Sizing in Weak Inversion |
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79 | (3) |
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Example 3.5 Sizing in Weak Inversion Given a Width Constraint |
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82 | (1) |
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3.1.6 Sizing Using the Drain Current Density |
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83 | (4) |
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Example 3.6 Sizing Using Contours in the JD and L Plane |
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87 | (3) |
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3.1.7 Inclusion of Extrinsic Capacitances |
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90 | (2) |
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Example 3.7 Iterative Sizing to Account for Self-Loading |
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92 | (22) |
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3.2 Practical Common-Source Stages |
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93 | (9) |
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94 | (1) |
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Example 3.8 Sizing a CS Stage with Active Load |
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95 | (3) |
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Example 3.9 Large-Signal Characteristic of a CS Stage with Active Load |
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98 | (1) |
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99 | (2) |
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Example 3.10 Sizing a CS Stage with Resistive Load |
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101 | (1) |
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3.3 Differential Amplifier Stages |
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102 | (11) |
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Example 3.11 Sizing a Differential Pair with Ideal Current Source Loads |
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105 | (3) |
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Example 3.12 Sizing a Differential Amplifier with Current-Mirror Load |
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108 | (3) |
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Example 3.13 Sizing a Differential Amplifier with Resistive Input Driver and Resistive Loads |
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111 | (2) |
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113 | (1) |
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113 | (1) |
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4 Noise, Distortion and Mismatch |
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114 | (51) |
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114 | (12) |
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4.1.1 Thermal Noise Modeling |
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114 | (3) |
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4.1.2 Tradeoff between Thermal Noise, GBW and Supply Current |
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117 | (1) |
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Example 4.1 Sizing of a Low-Noise IGS |
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118 | (1) |
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4.1.3 Thermal Noise from Active Loads |
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119 | (1) |
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Example 4.2 Choosing gm/ID of a p-Channel Load for Maximum Dynamic Range |
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120 | (1) |
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4.1.4 Flicker Noise (1/ƒ Noise) |
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121 | (4) |
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Example 4.3 Estimation of the Flicker Noise Corner Frequency |
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125 | (1) |
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126 | (24) |
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4.2.1 Nonlinearity of the MOS Transconductance |
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126 | (5) |
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4.2.2 Nonlinearity of the MOS Differential Pair |
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131 | (5) |
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Example 4.4 Sizing a Differential Amplifier Based on Distortion Specs |
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136 | (3) |
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4.2.3 Inclusion of the Output Conductance |
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139 | (7) |
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Example 4.5 Sizing of a Resistively Loaded CS Stage with Low HD2 |
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146 | (3) |
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Example 4.6 Sizing of a Resistively Loaded CS Stage with Low FfD2 and VDD = 1.2 V |
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149 | (1) |
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150 | (12) |
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4.3.1 Modeling of Random Mismatch |
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151 | (2) |
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4.3.2 Effect of Mismatch in a Current Mirror |
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153 | (1) |
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Example 4.7 Random Mismatch Estimation in a Current Mirror |
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154 | (5) |
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4.3.3 Effect of Mismatch in a Differential Amplifier |
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159 | (3) |
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Example 4.8 Offset Drift Estimation |
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162 | (1) |
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162 | (1) |
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163 | (2) |
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5 Practical Circuit Examples I |
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165 | (61) |
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5.1 Constant Transconductance Bias Circuit |
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165 | (6) |
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Example 5.1 Sizing of a Constant Transconductance Bias Circuit |
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168 | (3) |
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5.2 High-Swing Cascoded Current Mirror |
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171 | (6) |
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5.2.1 Sizing the Current Mirror Devices |
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174 | (1) |
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5.2.2 Sizing the Cascode Bias Circuit |
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175 | (2) |
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5.3 Low-Dropout Voltage Regulator |
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177 | (12) |
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5.3.1 Low-Frequency Analysis |
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180 | (1) |
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Example 5.2 Basic Sizing of an LDO |
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181 | (3) |
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5.3.2 High-Frequency Analysis |
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184 | (3) |
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Example 5.3 Sizing the LDO's Load Capacitance |
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187 | (2) |
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5.4 RF Low-Noise Amplifier |
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189 | (11) |
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5.4.1 Sizing for Low-Noise Figure |
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190 | (2) |
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Example 5.4 Sizing the LNA for a Given Noise Figure |
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192 | (4) |
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5.4.2 Sizing for Low-Noise Figure and Low Distortion |
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196 | (1) |
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Example 5.5 Sizing the LNA for Minimum HD2 |
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197 | (3) |
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200 | (14) |
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201 | (3) |
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5.5.2 Optimization Assuming Constant Transit Frequency |
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204 | (1) |
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5.5.3 Optimization Assuming Constant Drain Current |
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205 | (1) |
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Example 5.6 Charge Amplifier Optimization (Constant ID) |
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205 | (2) |
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5.5.4 Optimization Assuming Constant Noise and Bandwidth |
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207 | (2) |
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Example 5.7 Charge Amplifier Optimization (Constant Noise and Bandwidth) |
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209 | (1) |
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Example 5.8 Charge Amplifier Sizing |
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210 | (3) |
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Example 5.9 Charge Amplifier Re-sizing for Smaller Area |
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213 | (1) |
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5.6 Designing for Process Corners |
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214 | (10) |
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5.6.1 Biasing Considerations |
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214 | (2) |
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5.6.2 Technology Evaluation over Process and Temperature |
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216 | (4) |
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Example 5.10 Constant Transconductance Bias Circuit Performance across Process Corners |
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220 | (1) |
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5.6.3 Possible Design Flows |
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221 | (1) |
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Example 5.11 Design of a Charge Amplifier with Corner Awareness |
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222 | (2) |
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224 | (1) |
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225 | (1) |
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6 Practical Circuit Examples II |
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226 | (96) |
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6.1 Basic OTA for Switched-Capacitor Circuits |
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226 | (23) |
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6.1.1 Small-Signal Circuit Analysis |
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226 | (5) |
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6.1.2 Optimization Assuming Constant Noise and Bandwidth |
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231 | (2) |
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Example 6.1 Optimization of the Basic OTA |
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233 | (4) |
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Example 6.2 Sizing of the Basic OTA |
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237 | (5) |
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6.1.3 Optimization in Presence of Slewing |
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242 | (3) |
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Example 6.3 Sizing of the Basic OTA Circuit in Presence of Slewing |
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245 | (4) |
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6.2 Folded-Cascode OTA for Switched-Capacitor Circuits |
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249 | (18) |
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249 | (6) |
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6.2.2 Optimization Procedure |
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255 | (1) |
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Example 6.4 Sizing of the Folded-Cascode Output Branch |
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255 | (3) |
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Example 6.5 Optimization of the Folded-Cascode OTA |
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258 | (4) |
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Example 6.6 Sizing the Folded-Cascode OTA |
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262 | (4) |
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6.2.3 Optimization in Presence of Slewing |
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266 | (1) |
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6.3 Two-Stage OTA for Switched-Capacitor Circuits |
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267 | (16) |
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268 | (2) |
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6.3.2 Optimization Procedure |
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270 | (2) |
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Example 6.7 Optimization of the Two-Stage OTA |
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272 | (5) |
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Example 6.8 Sizing the Two-Stage OTA |
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277 | (4) |
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6.3.3 Optimization in Presence of Slewing |
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281 | (2) |
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6.4 Simplified Design Flows |
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283 | (2) |
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284 | (1) |
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284 | (1) |
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285 | (4) |
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Example 6.9 Sizing a Transmission Gate Switch |
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288 | (1) |
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289 | (1) |
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290 | (2) |
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Appendix 1 The EKV Parameter Extraction Algorithm |
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292 | (11) |
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A.1.1 Review of Equations |
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292 | (1) |
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A.1.2 Parameter Extraction Algorithm |
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292 | (2) |
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A.1.3 Matlab Function XTRACT.m |
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294 | (1) |
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A.1.4 Parameter Extraction Example |
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294 | (3) |
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A.1.5 Matlab Function XTRACT2.m |
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297 | (2) |
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A.1.6 Corner Parameter Extraction |
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299 | (3) |
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302 | (1) |
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302 | (1) |
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Appendix 2 Lookup Table Generation and Usage |
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303 | (12) |
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A.2.1 Lookup Table Generation |
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303 | (2) |
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A.2.1.1 Configuration File |
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305 | (2) |
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A.2.1.2 Generating Lookup Tables for a New Technology |
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307 | (1) |
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A.2.2 Matlab Function lookup.m |
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307 | (2) |
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A.2.3 Matlab Function lookupVGS.m |
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309 | (1) |
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A.2.4 Lookup of Ratios with Non-monotonic Vectors |
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310 | (3) |
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A.2.5 LookupVGS with Non-monotonic gm/ID Vector |
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313 | (1) |
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A.2.6 Passing Design Variables to the Simulator |
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313 | (1) |
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314 | (1) |
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Appendix 3 Layout Dependence |
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315 | (7) |
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A.3.1 Introduction to Layout Dependent Effects (LDE) |
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315 | (1) |
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A.3.2 Transistor Finger Partitioning |
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316 | (1) |
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A.3.3 Width Dependence of Parameter Ratios |
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317 | (4) |
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321 | (1) |
Index |
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