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E-raamat: Systematic Design of Analog IP Blocks

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Systematic Design of Analog IP BlocksSuurem pilt
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A current paradox in the semiconductor industry is that digital tools have peaked in keeping pace with technology as components further shrink, while just emerging analog tools create bottlenecks in the alien digital environment. In addressing these design and productivity challenges, this work introduces a design methodology for integrated analog solutions in affordable design times. After overviewing the analog design process and categories of IP designs, the authors validate these methodologies via three "industrial-strength" experiments on applications; design times and performance are reported. Lacks an index. Annotation (c) Book News, Inc., Portland, OR (booknews.com)

Systematic Design of Analog IP Blocks introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified: commodity IP and star IP. Each category requires a different approach to boost design productivity. Commodity IP blocks are well suited to be automated in an analog synthesis environment and provided as soft IP. The design knowledge is usually common knowledge, and reuse is high accounting for the setup time needed for the analog library. Star IP still changes as technology evolves and the design cost can only be reduced by following a systematic design approach supported by point tools to relieve the designer from error-prone, repetitive tasks, allowing him/her to focus on new ideas to push the limits of the design.

This book introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified. To validate the presented methodologies, the authors have selected and designed accordingly three different industrial-strength applications.

Arvustused

From the reviews:









"This book addresses the problem of how to bridge efficiently the analog design productivity gap. The style of presentation is high, but clear. This valuable book is timely and well written. This book may be useful for graduate-level students in Electrical Engineering, as well as engineers and researchers who are familiar with mixed signal SoC design. I would like to certainly fully recommend this book to all SoC designers looking for a very up-to-date text of analog IP blocks." (Mile Stojcev, Microelectronics Reliability, Vol. 45, 2005)

Abbreviations ix
Preface xi
Chapter 1 Introduction 1(10)
1.1 Moore's law and the ITRS roadmap revisited
1(2)
1.2 Bridging the productivity gap
3(5)
1.2.1 Analog design productivity
4(2)
1.2.2 Analog IP
6(2)
1.3 Goals of this work
8(1)
1.4 Outline of this work
8(3)
Chapter 2 Design Methodologies for analog IP 11(24)
2.1 Used terminology
11(1)
2.2 The analog design process
12(2)
2.3 Overview of Analog Design Automation
14(4)
2.3.1 Plan-based sizing
15(1)
2.3.2 Simulation-based sizing
16(1)
2.3.3 Equation-based sizing
16(2)
2.3.3.1 Geometric programming
16(1)
2.3.3.2 The AMGIE framework
17(1)
2.3.4 Research
18(1)
2.4 Commodity IP vs. star IP
18(4)
2.4.1 Commodity IP
19(1)
2.4.2 Star IP
19(3)
2.5 The MONDRIAAN toolset
22(12)
2.5.1 Requirements of the MONDRIAAN toolset
23(1)
2.5.2 Description of the Layout Model
24(2)
2.5.3 Description of the Layout Generation Methodology
26(3)
2.5.4 Productivity gain through the MONDRIAAN toolset
29(13)
2.5.4.1 Current-steering D/A converter modules
30(3)
2.5.4.2 Interpolating/averaging A/D converter modules
33(1)
2.6 Conclusions
34(1)
Chapter 3 Systematic Design of a Particle Detector Front-End 35(48)
3.1 Introduction
35(2)
3.2 PDFE design flow
37(1)
3.3 PDFE architecture
38(3)
3.4 Behavioral modeling for system-level specification phase
41(1)
3.5 PDFE Design phase
3.5.1 PDFE architectural-level synthesis
42(7)
3.5.1.2 Specifications for the building blocks
47(2)
3.5.2 CSA-PSA circuit-level synthesis
49(29)
3.5.2.1 The CSA-PSA architecture
49(1)
3.5.2.2 The Charge Sensitive Amplifier
50(10)
3.5.2.3 The Pulse-Shaping Amplifier with pole-zero cancellation
60(5)
3.5.2.4 CSA-PSA sensitivity analysis
65(1)
3.5.2.5 CSA-PSA noise analysis
66(6)
3.5.2.6 The CSA-PSA as soft IP library cell
72(5)
3.6 Layout
77(1)
3.7 Extracted model for verification
78(1)
3.8 Experimental results
78(4)
3.8.1 Functional Testing
79(2)
3.8.2 Radiation Testing
81(1)
3.9 Conclusions
82(1)
Chapter 4 Systematic Design of CMOS Current-Steering DIA converters 83(56)
4.1 Introduction
83(2)
4.2 D/A converter Design Flow
85(1)
4.3 Current-steering DIA converter architecture
86(3)
4.4 Behavioral Modeling for the Specification Phase
89(4)
4.4.1 Dynamic behavior
89(2)
4.4.2 Static behavior
91(1)
4.4.3 Power and Area Estimators
92(1)
4.5 Design Phase
93(17)
4.5.1 Architectural-level synthesis
93(3)
4.5.1.1 Static performance
93(1)
4.5.1.2 Dynamic performance
94(2)
4.5.2 Module-level synthesis
96(9)
4.5.2.1 Overview of switching schemes
96(3)
4.5.2.2 Compensating graded and systematic errors
99(6)
4.5.3 Circuit-level synthesis
105(4)
4.5.3.1 Static Performance
105(2)
4.5.3.2 Dynamic performance
107(2)
4.5.3.3 Sizing Plan
109(1)
4.5.4 Full Decoder Synthesis
109(1)
4.5.5 Clock Driver Synthesis
110(1)
4.6 Layout Generation
110(3)
4.6.1 Floorplanning
111(1)
4.6.2 Circuit and Module Layout Generation
111(1)
4.6.2.1 Current-source array Layout Generation
112(1)
4.6.2.2 Swatch Array Layout Generation
112(1)
4.6.2.3 Full Decoder Standard Cell Place and Route
112(1)
4.6.3 Layout Assembly
112(1)
4.7 Extracted (A)HDL model for verification
113(3)
4.7.1 Dynamic behavior
113(1)
4.7.2 Static behavior
113(3)
4.7.3 Power and Area Estimators
116(1)
4.8 Experimental Results
116(1)
4.9 A 12-bit 200 MS/s CMOS DIA converter
117(9)
4.9.1 Introduction
117(1)
4.9.2 D/A converter Architecture
117(1)
4.9.3 DIA converter Synthesis
118(6)
4.9.4 Conclusions
124(2)
4.10 A 14-bit 150 MS/s Q2 Random Walk CMOS DIA converter
126(11)
4.10.1 Introduction
126(1)
4.10.2 DIA converter Architecture
127(1)
4.10.3 DIA converter Synthesis
128(9)
4.10.4 Conclusions
137(1)
4.11 Conclusions on DIA converter Methodology
137(2)
Chapter 5 Systematic Design of an Interpolating/Averaging A/D Converter 139(40)
5.1 Introduction
139(1)
5.2 High-speed A/D converter architectures
140(6)
5.2.1 The flash architecture
141(4)
5.2.2 The pipelined architecture
145(1)
5.2.3 Two-step architectures
145(1)
5.3 A/D Converter Design Flow
146(1)
5.4 The interpolating/averaging architecture
147(3)
5.5 Behavioral Modeling for the Specification Phase
150(1)
5.6 Design phase
151(19)
5.6.1 Architectural-level synthesis
151(5)
5.6.1.1 Static performance
151(1)
5.6.1.2 Dynamic performance
152(4)
5.6.2 Circuit-level synthesis
156(14)
5.6.2.1 Sample and hold
157(2)
5.6 2.2 Reference ladder network
159(1)
5.6.2.3 Preamplifier stage 1
160(2)
5.6.2.4 Preamplifier stage 2
162(1)
5.6.2.5 Comparator and digital back-end
163(3)
5.6.2.6 Sizing plan
166(4)
5.7 Layout
170(1)
5.8 Verification Phase
171(2)
5.9 Experimental Results
173(4)
5.10 Conclusions
177(2)
Chapter 6 General Conclusions 179(4)
Bibliography 183


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