Preface |
|
xi | |
1 Radio System Architectures |
|
1 | (30) |
|
1.1 Radio System Architectures |
|
|
2 | (3) |
|
1.1.1 Tasks of a Radio Receiver |
|
|
3 | (1) |
|
|
4 | (1) |
|
1.2 Heterodyne Structures |
|
|
5 | (5) |
|
1.2.1 Benefits and Drawbacks of Heterodyne Receivers |
|
|
7 | (1) |
|
1.2.2 Image Removal with RF Filter |
|
|
8 | (1) |
|
1.2.3 Multiple Conversion Receivers |
|
|
8 | (1) |
|
1.2.4 IF Filter Technologies |
|
|
9 | (1) |
|
1.3 Complex Mixer: I/Q Processing and Image Rejection |
|
|
10 | (5) |
|
1.3.1 Single Sideband Transmitter |
|
|
11 | (1) |
|
1.3.2 Image Rejection Mixer |
|
|
12 | (3) |
|
1.4 Zero IF and Low IF Structures |
|
|
15 | (2) |
|
1.5 Digital and Software-Defined Radio Systems |
|
|
17 | (10) |
|
1.5.1 Mixing and Sampling |
|
|
19 | (2) |
|
1.5.2 Subsampling and Folding |
|
|
21 | (1) |
|
1.5.3 Sampling Signals with Spurious Components and Noise |
|
|
22 | (1) |
|
1.5.4 Frequency Division Multiplexing Channel Separation |
|
|
22 | (1) |
|
1.5.5 Effect of Sampling Jitter |
|
|
23 | (2) |
|
1.5.6 How Many Bits Are Required? |
|
|
25 | (1) |
|
1.5.7 Direct Radio Frequency Sampling |
|
|
26 | (1) |
|
1.6 Complete Transceiver Architectures |
|
|
27 | (2) |
|
|
29 | (1) |
|
|
29 | (2) |
2 Transistor RF Amplifiers |
|
31 | (58) |
|
|
32 | (1) |
|
2.2 Small-Signal Amplifiers |
|
|
33 | (21) |
|
2.2.1 Amplifier Bias Network |
|
|
34 | (5) |
|
2.2.2 Small-Signal Models |
|
|
39 | (1) |
|
2.2.3 High-Frequency Transistor Models |
|
|
40 | (2) |
|
2.2.4 Single-Stage Configurations |
|
|
42 | (4) |
|
2.2.5 Analysis of a Common Emitter Amplifier |
|
|
46 | (4) |
|
2.2.6 Nonlinearity and Distortion |
|
|
50 | (3) |
|
2.2.7 SPICE Transistor Models |
|
|
53 | (1) |
|
2.3 Low-Noise Amplifiers for RF Receivers |
|
|
54 | (12) |
|
|
57 | (6) |
|
|
63 | (3) |
|
2.4 Power Amplifiers for RF Transmitters |
|
|
66 | (17) |
|
2.4.1 Power Amplifiers Figures of Merit |
|
|
66 | (5) |
|
2.4.2 Power Amplifier Classes |
|
|
71 | (5) |
|
2.4.3 High-Efficiency PAs: Switching and Harmonic Tuning |
|
|
76 | (4) |
|
2.4.4 Efficiency in Back-Off: Doherty and Envelope Tracking |
|
|
80 | (3) |
|
|
83 | (3) |
|
|
86 | (2) |
|
|
88 | (1) |
3 Frequency Conversion Circuits |
|
89 | (40) |
|
|
89 | (30) |
|
3.1.1 Mixer Figures of Merit |
|
|
94 | (2) |
|
3.1.2 Mixer Architectures |
|
|
96 | (5) |
|
|
101 | (5) |
|
3.1.4 Diode Passive Mixers |
|
|
106 | (4) |
|
3.1.5 Transistor Passive Mixers |
|
|
110 | (3) |
|
3.1.6 Transistor Active Mixers |
|
|
113 | (3) |
|
3.1.7 Mixer Nonidealities |
|
|
116 | (3) |
|
3.2 Frequency Multipliers |
|
|
119 | (8) |
|
3.2.1 Frequency Multipliers Figures of Merit |
|
|
120 | (1) |
|
3.2.2 Frequency Multiplier Architectures |
|
|
121 | (1) |
|
3.2.3 Diode-Based Frequency Multipliers |
|
|
122 | (4) |
|
3.2.4 Transistor-Based Frequency Multipliers |
|
|
126 | (1) |
|
|
127 | (1) |
|
|
128 | (1) |
4 Phase-Locked Loops: Operation, Circuits, and Applications |
|
129 | (66) |
|
4.1 Analysis of PLL Systems |
|
|
130 | (11) |
|
|
130 | (1) |
|
4.1.2 PLL Linear Analysis |
|
|
131 | (2) |
|
4.1.3 PLL Transfer Function |
|
|
133 | (4) |
|
4.1.4 Steady State Phase Error |
|
|
137 | (4) |
|
4.2 Phase-Frequency Behavior |
|
|
141 | (12) |
|
4.2.1 Loop Analysis and Butterfly Diagram |
|
|
141 | (3) |
|
4.2.2 Capture Range and Lock Range |
|
|
144 | (3) |
|
4.2.3 PLL Equivalent Noise Bandwidth |
|
|
147 | (6) |
|
4.3 Phase Detectors and Voltage-Controlled Oscillators |
|
|
153 | (10) |
|
4.3.1 Phase Detectors for Analog Signals |
|
|
153 | (2) |
|
4.3.2 Phase Detectors for Digital Signals |
|
|
155 | (2) |
|
4.3.3 Mixed-Signals Phase Detectors |
|
|
157 | (3) |
|
|
160 | (3) |
|
|
163 | (19) |
|
4.4.1 FM and AM Demodulation |
|
|
163 | (4) |
|
4.4.2 Coherent AM Demodulation |
|
|
167 | (2) |
|
4.4.4 Digital Modulation and Demodulation |
|
|
169 | (4) |
|
4.4.5 Frequency Synthesizers |
|
|
173 | (2) |
|
4.4.6 Direct Digital Synthesizers |
|
|
175 | (4) |
|
4.4.7 Data Resynchronization and Clock/Data Recovery |
|
|
179 | (3) |
|
4.5 Examples of Integrated PLLs |
|
|
182 | (10) |
|
4.5.1 General Purpose PLL: CD4046 |
|
|
183 | (3) |
|
4.5.2 Tone Decoder PLL: NE567 |
|
|
186 | (5) |
|
|
191 | (1) |
|
|
192 | (2) |
|
|
194 | (1) |
|
|
194 | (1) |
5 Analog-to-Digital and Digital-to-Analog Conversion |
|
195 | (76) |
|
5.1 Digital Representation of Analog Quantities |
|
|
196 | (16) |
|
5.1.1 Analog Quantities and Digital Quantities |
|
|
196 | (1) |
|
|
197 | (5) |
|
5.1.3 Quantization Process |
|
|
202 | (6) |
|
5.1.4 Analog-to-Digital Conversion Systems |
|
|
208 | (4) |
|
5.2 Digital-to-Analog Converters |
|
|
212 | (15) |
|
5.2.1 Static and Dynamic Parameters |
|
|
212 | (1) |
|
5.2.2 Errors in Digital-to-Analog Converters |
|
|
213 | (4) |
|
5.2.3 Circuits for Digital-to-Analog Conversion |
|
|
217 | (10) |
|
5.3 Analog-to-Digital Conversion: Basic Techniques |
|
|
227 | (17) |
|
5.3.1 Static and Dynamic Parameters |
|
|
228 | (3) |
|
5.3.2 ADC Taxonomy and Basic Structures |
|
|
231 | (5) |
|
5.3.3 Mixed ADC Architectures |
|
|
236 | (8) |
|
5.4 Analog-to-Digital Converters for Specific Applications |
|
|
244 | (11) |
|
5.4.1 Oversampling and Differential Converters |
|
|
244 | (5) |
|
5.4.2 Logarithmic Analog-to-Digital Converters |
|
|
249 | (4) |
|
|
253 | (2) |
|
|
255 | (15) |
|
|
256 | (1) |
|
|
257 | (3) |
|
|
260 | (1) |
|
|
261 | (2) |
|
|
263 | (5) |
|
5.5.6 Total ADC System Errors and ENOB |
|
|
268 | (2) |
|
|
270 | (1) |
Selected Bibliography |
|
271 | (2) |
Acronyms and Abbreviations |
|
273 | (4) |
List of Symbols |
|
277 | (4) |
About the Authors |
|
281 | (2) |
Index |
|
283 | |