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E-raamat: Test and Diagnosis of Analogue, Mixed-signal and RF Integrated Circuits: The system on chip approach

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  • Sari: Materials, Circuits and Devices
  • Ilmumisaeg: 23-Sep-2011
  • Kirjastus: Institution of Engineering and Technology
  • Keel: eng
  • ISBN-13: 9780863419997
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  • Formaat: PDF+DRM
  • Sari: Materials, Circuits and Devices
  • Ilmumisaeg: 23-Sep-2011
  • Kirjastus: Institution of Engineering and Technology
  • Keel: eng
  • ISBN-13: 9780863419997
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Systems on Chip (SoC) for communications, multimedia and computer applications have recently received much international attention; one such example being the single-chip transceiver. Modern microelectronic design adopts a mixed-signal approach as a complex SoC is a mixed-signal system including both analogue and digital circuits. Automatic testing becomes crucially important to drive down the overall cost of next generation SoC devices. Test and fault diagnosis of analogue, mixed-signal and RF circuits, however, proves much more difficult than that of digital circuits due to tolerances, parasitics and nonlinearities and therefore, together with challenging tuning and calibration, remains the bottleneck for automatic SoC testing. This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective. An essential reference companion to researchers and engineers in mixed-signal testing, the book can also be used as a text for postgraduate and senior undergraduate students.
Preface xv
List of contributors
xix
Fault diagnosis of linear and non-linear analogue circuits
1(36)
Yichuang Sun
Introduction
1(2)
Multiple-fault diagnosis of linear circuits
3(12)
Fault incremental circuit
3(1)
Branch-fault diagnosis
4(2)
Testability analysis and design for testability
6(2)
Bilinear function and multiple excitation method
8(1)
Node-fault diagnosis
9(1)
Parameter identification after k-node fault location
10(2)
Cutset-fault diagnosis
12(3)
Tolerance effects and treatment
15(1)
Class-fault diagnosis of analogue circuits
15(6)
Class-fault diagnosis and general algebraic method for classification
16(2)
Class-fault diagnosis and topological technique for classification
18(1)
t-class-fault diagnosis and topological method for classification
19(2)
Fault diagnosis of non-linear circuits
21(8)
Fault modelling and fault incremental circuits
21(3)
Fault location and identification
24(2)
Alternative fault incremental circuits and fault diagnosis
26(3)
Recent advances in fault diagnosis of analogue circuits
29(3)
Test node selection and test signal generation
29(1)
Symbolic approach for fault diagnosis of analogue circuits
30(1)
Neural-network-and wavelet-based methodsfor analogue fault diagnosis
31(1)
Hierarchical approach for large-scale circuit fault diagnosis
31(1)
Summary
32(1)
References
33(4)
Symbolic function approaches for analogue fault diagnosis
37(46)
Stefano Manetti
Maria Cristina Piccirlli
Introduction
37(2)
Symbolic analysis
39(2)
Symbolic analysis techniques
40(1)
The SAPWIN program
40(1)
Testability and ambiguity groups
41(16)
Algorithms for testability evaluation
42(5)
Ambiguity groups
47(5)
Singular-value decomposition approach
52(5)
Testability analysis of non-linear circuts
57(1)
Fault diagnosis of linear analogue circutis
57(14)
Techniques based on bilinear decomposition of fault equations
59(3)
Newton-Raphson-based approach
62(5)
Selection of the test frequencies
67(4)
Fault diagnosis of non-linear circuits
71(6)
PWL models
72(1)
Transient analysis models for reactive components
73(1)
The Katznelson-type algorithm
73(1)
Circuit fault diagnosis application
74(1)
The SAPDEC program
75(2)
Conclusions
77(1)
References
77(6)
Neural-network-based approaches for analogue circuit fault diagnosis
83(30)
Yichuang Sun
Yigang He
Introduction
83(1)
Fault diagnosis of analogue circuits with tolerances using artificail neural networks
84(10)
Artificial neural networks
85(2)
Fault diagnosis of analogue circuits
87(1)
Fault diagnosis using ANNs
88(2)
Neural-network approach for fault diagnosis of large-scale analogue circuits
90(1)
Illustrative examples
90(4)
Wavelet-based neural-network technique for fault diagnosis of analogue circuits with noise
94(6)
Wavelet decomposition
94(1)
Wavelet feature extraction of noise signals
95(1)
WNNs
96(1)
WNN algorithm for fault diagnosis
97(1)
Example circuits and results
98(2)
Neural-network-based L1-norm optimization approach for fault diagnosis of non-linear circuits
100(10)
L1-norm optimization approach for fault location of non-linear circuits
103(2)
NNs applied to L1-norm fault diagnosis of non-linear circuits
105(4)
Illustrative example
109(1)
Summary
110(1)
References
111(2)
Hierarchical/decomposition techniques for large-scale analogue diagnosis
113(28)
Peter Shephered
Introduction
113(2)
Diagnosis definitions
114(1)
Background to analogue fault diagnosis
115(6)
Simulation before test
115(1)
Simulation after test
116(5)
Hierarchical techniques
121(16)
Simulation after test
121(10)
Simulation before test
131(4)
Mixed SBT/SAT approaches
135(2)
Conclusions
137(1)
References
138(3)
DFT and BIST techniques for analogue and mixed-signal test
141(38)
Mona Safi-Harb
Gordon Roberts
Introduction
141(1)
Background
142(4)
Signal generation
146(5)
Direct digital frequency synthesis
146(1)
Oscillator-based approaches
147(1)
Memory-based signal generation
148(1)
Multi-tones
149(1)
Area overhead
150(1)
Signal capture
151(3)
Timing measurements and jitter analysers
154(10)
Single counter
154(1)
Analogue-based interpolation techniques: time-to-voltage converter
155(1)
Digital phase-initerpolation techniques: delay line
156(1)
Vernier delay line
157(2)
Component-invariant VDL for jitter measurement
159(1)
Analogue-based jitter measurement device
160(2)
Time amplification
162(1)
PLL and DLL- injection methods for PLL tests
163(1)
Calibration techniques for TMU and TDC
164(2)
Complete on-chip test core: proposed architecture in Reference 11 and its versatile applications
166(6)
Attractive and flexible architecture
166(2)
Oscilloscope/curve tracing
168(1)
Coherent sampling
169(1)
Time domain reflectometry/transmission
169(1)
Crosstalk
169(1)
Supply/substrate noise
170(1)
RF testing-amplifier resonance
171(1)
Limitations of the proposed architecture in Reference 11
172(1)
Recent trends
172(1)
Conclusions
173(1)
References
174(5)
Design-for-testability of analogue filters
179(34)
Yichuang Sun
Masood-ul Hasan
Introduction
179(2)
DfT by bypassing
181(7)
Bypassing by bandwidth broadening
181(5)
Bypassing using duplicated/switched opamp
186(2)
DfT by multiplexing
188(4)
Tow-Thomas biquad filter
188(1)
The Kerwin-Huelsman-Newcomb biquad filter
189(1)
Second-order OTA-C filter
190(2)
OBT of analogue filters
192(9)
Test transformation of active-RC filters
193(3)
OBT of OTA-C filters
196(3)
OBT of SC biquadratic filter
199(2)
Testing of high-order analogue filters
201(9)
Testing of high-order filters using bypassing
202(1)
Testing of high-order cascade filters using multiplexing
203(2)
Test of MLF OTA-C filters using multiplexing
205(2)
OBT structures for high-order OTA-C filters
207(3)
Summary
210(1)
References
210(3)
Test of A/D converters: From converter characteristics to built-in self-test proposals
213(22)
Andreas Lechner
Andrew Richardson
Introduction
213(1)
A/D conversion
214(6)
Static A/D converter performance parameters
216(2)
Dynamic A/D converter performance parameters
218(2)
A/D converter test approaches
220(8)
Set-up for A/D converter test
220(1)
Capturing the test response
221(1)
Static performance parameter test
222(4)
Dynamic performance parameter test
226(2)
A/D converter built-in self-test
228(3)
Summary and conclusions
231(1)
References
232(3)
Test of Σ Δ converters
235(42)
Gildas Leger
Adoracion Rueda
Introduction
235(1)
An overview of Σ Δ modulation: opening the ADC black box
236(7)
Principle of operation: Σ Δ modulation and noise shaping
236(2)
Digital filtering and decimation
238(1)
Σ Δ modulator architecture
239(4)
Characterization of Σ Δ Converters
243(11)
Congsequences of Σ Δ modulation for ADC characterization
243(1)
Static performance
244(2)
Dynamic performance
246(2)
Applying a FFT with success
248(6)
Test of Σ Δ converters
254(5)
Limitations of the functional approach
255(1)
The built-in self-test approach
255(4)
Model-based testing
259(12)
Model-based test concepts
259(3)
Polynomial model-based BIST
262(2)
Behavioural model-based BIST
264(7)
Conclusions
271(2)
References
273(4)
Phase-locked loop test methodologies: Current characterization and production test practices
277(32)
Martin John Burbidge
Andrew Richardson
Introduction: Phase-locked loop operation and test motivations
277(10)
PLL key elements' operation and test issues
277(5)
Typical CP-PLL test specifications
282(5)
Traditional test techniques
287(14)
Characterization focused tests
287(11)
Production test focused
298(3)
BIST techniques
301(5)
Summary and conclusions
306(1)
References
306(3)
On-chip testing techniques for RF wireless transcelver system and components
309(38)
Alberto Valdes-Garcia
Jose Silva-Martinez
Edgar Sanchez-Sinencio
Introduction
309(2)
Frequency-response test system for analogue baseband circuits
311(13)
Principle of operation
311(2)
Testing methodology
313(1)
Implementation as a complete on-chip test system with a digital interface
314(5)
Experimental evaluation of the FRCS
319(5)
CMOS amplitude detector for on-chip testing of RF circuits
324(9)
Gain and 1-dB compression point measurement with amplitude detectors
327(1)
CMOS RF amplitude detector design
328(2)
Experimental results
330(3)
Architecture for on-chip testing of wireless transceivers
333(9)
Switched loop-back architecture
333(4)
Overall testing strategy
337(2)
Simulation results
339(3)
Summary and outlook
342(1)
References
343(4)
Tuning and calibration of analogue, mixed-signal and RF circuits
347(36)
James Moritz
Yichuang Sun
Introduction
347(1)
On-chip filter tuning
348(17)
Tuning system requirements for on-chip filters
348(1)
Frequency tuning and Q tuning
349(3)
Online and offline tuning
352(2)
Master-slave tuning
354(1)
Frequency tuning methods
355(4)
Q tuning techniques
359(1)
Tuning of high-order leapfrog filters
360(5)
Self-calibration techniques for PLL frequency synthesizers
365(6)
Need for calibration in PLL synthesizers
365(1)
PLL synthesizer with calibrated VCO
366(2)
Automatic PLL calibration
368(2)
Other PLL synthesizer calibration applications
370(1)
On-chip antenna impedance matching
371(7)
Requirement for on-chip antenna impedance matching
371(2)
Matching network
373(3)
Impedance sensors
376(1)
Tuning algorithms
377(1)
Conclusions
378(1)
References
378(5)
Index 383
Yichuang Sun received his Ph.D. from the University of York and is currently Professor at the University of Hertfordshire. His research interests are in analogue and mixed-signal, RF and communication circuits, circuit testing and fault diagnosis, coding and signal detection, space-time and MIMO communications, and wireless and mobile networks. He has published three books and over 180 papers. Professor Sun has been a book series editor for the IET, guest editor of four special issues for IET journals, and Track Chair and committee member for many international conferences. He is editor of ETRI Journal of South Korea and serves on several IEEE committees.