Preface |
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xv | |
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xix | |
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Fault diagnosis of linear and non-linear analogue circuits |
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1 | (36) |
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1 | (2) |
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Multiple-fault diagnosis of linear circuits |
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3 | (12) |
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Fault incremental circuit |
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3 | (1) |
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4 | (2) |
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Testability analysis and design for testability |
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6 | (2) |
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Bilinear function and multiple excitation method |
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8 | (1) |
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9 | (1) |
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Parameter identification after k-node fault location |
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10 | (2) |
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12 | (3) |
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Tolerance effects and treatment |
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15 | (1) |
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Class-fault diagnosis of analogue circuits |
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15 | (6) |
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Class-fault diagnosis and general algebraic method for classification |
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16 | (2) |
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Class-fault diagnosis and topological technique for classification |
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18 | (1) |
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t-class-fault diagnosis and topological method for classification |
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19 | (2) |
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Fault diagnosis of non-linear circuits |
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21 | (8) |
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Fault modelling and fault incremental circuits |
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21 | (3) |
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Fault location and identification |
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24 | (2) |
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Alternative fault incremental circuits and fault diagnosis |
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26 | (3) |
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Recent advances in fault diagnosis of analogue circuits |
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29 | (3) |
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Test node selection and test signal generation |
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29 | (1) |
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Symbolic approach for fault diagnosis of analogue circuits |
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30 | (1) |
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Neural-network-and wavelet-based methodsfor analogue fault diagnosis |
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31 | (1) |
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Hierarchical approach for large-scale circuit fault diagnosis |
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31 | (1) |
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32 | (1) |
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33 | (4) |
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Symbolic function approaches for analogue fault diagnosis |
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37 | (46) |
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37 | (2) |
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39 | (2) |
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Symbolic analysis techniques |
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40 | (1) |
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40 | (1) |
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Testability and ambiguity groups |
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41 | (16) |
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Algorithms for testability evaluation |
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42 | (5) |
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47 | (5) |
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Singular-value decomposition approach |
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52 | (5) |
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Testability analysis of non-linear circuts |
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57 | (1) |
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Fault diagnosis of linear analogue circutis |
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57 | (14) |
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Techniques based on bilinear decomposition of fault equations |
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59 | (3) |
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Newton-Raphson-based approach |
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62 | (5) |
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Selection of the test frequencies |
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67 | (4) |
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Fault diagnosis of non-linear circuits |
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71 | (6) |
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72 | (1) |
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Transient analysis models for reactive components |
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73 | (1) |
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The Katznelson-type algorithm |
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73 | (1) |
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Circuit fault diagnosis application |
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74 | (1) |
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75 | (2) |
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77 | (1) |
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77 | (6) |
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Neural-network-based approaches for analogue circuit fault diagnosis |
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83 | (30) |
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83 | (1) |
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Fault diagnosis of analogue circuits with tolerances using artificail neural networks |
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84 | (10) |
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Artificial neural networks |
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85 | (2) |
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Fault diagnosis of analogue circuits |
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87 | (1) |
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Fault diagnosis using ANNs |
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88 | (2) |
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Neural-network approach for fault diagnosis of large-scale analogue circuits |
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90 | (1) |
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90 | (4) |
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Wavelet-based neural-network technique for fault diagnosis of analogue circuits with noise |
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94 | (6) |
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94 | (1) |
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Wavelet feature extraction of noise signals |
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95 | (1) |
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96 | (1) |
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WNN algorithm for fault diagnosis |
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97 | (1) |
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Example circuits and results |
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98 | (2) |
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Neural-network-based L1-norm optimization approach for fault diagnosis of non-linear circuits |
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100 | (10) |
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L1-norm optimization approach for fault location of non-linear circuits |
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103 | (2) |
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NNs applied to L1-norm fault diagnosis of non-linear circuits |
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105 | (4) |
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109 | (1) |
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110 | (1) |
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111 | (2) |
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Hierarchical/decomposition techniques for large-scale analogue diagnosis |
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113 | (28) |
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113 | (2) |
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114 | (1) |
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Background to analogue fault diagnosis |
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115 | (6) |
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115 | (1) |
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116 | (5) |
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121 | (16) |
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121 | (10) |
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131 | (4) |
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135 | (2) |
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137 | (1) |
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138 | (3) |
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DFT and BIST techniques for analogue and mixed-signal test |
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141 | (38) |
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141 | (1) |
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142 | (4) |
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146 | (5) |
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Direct digital frequency synthesis |
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146 | (1) |
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Oscillator-based approaches |
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147 | (1) |
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Memory-based signal generation |
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148 | (1) |
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149 | (1) |
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150 | (1) |
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151 | (3) |
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Timing measurements and jitter analysers |
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154 | (10) |
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154 | (1) |
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Analogue-based interpolation techniques: time-to-voltage converter |
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155 | (1) |
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Digital phase-initerpolation techniques: delay line |
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156 | (1) |
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157 | (2) |
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Component-invariant VDL for jitter measurement |
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159 | (1) |
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Analogue-based jitter measurement device |
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160 | (2) |
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162 | (1) |
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PLL and DLL- injection methods for PLL tests |
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163 | (1) |
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Calibration techniques for TMU and TDC |
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164 | (2) |
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Complete on-chip test core: proposed architecture in Reference 11 and its versatile applications |
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166 | (6) |
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Attractive and flexible architecture |
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166 | (2) |
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Oscilloscope/curve tracing |
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168 | (1) |
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169 | (1) |
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Time domain reflectometry/transmission |
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169 | (1) |
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169 | (1) |
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170 | (1) |
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RF testing-amplifier resonance |
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171 | (1) |
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Limitations of the proposed architecture in Reference 11 |
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172 | (1) |
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172 | (1) |
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173 | (1) |
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174 | (5) |
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Design-for-testability of analogue filters |
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179 | (34) |
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179 | (2) |
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181 | (7) |
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Bypassing by bandwidth broadening |
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181 | (5) |
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Bypassing using duplicated/switched opamp |
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186 | (2) |
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188 | (4) |
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188 | (1) |
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The Kerwin-Huelsman-Newcomb biquad filter |
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189 | (1) |
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Second-order OTA-C filter |
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190 | (2) |
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192 | (9) |
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Test transformation of active-RC filters |
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193 | (3) |
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196 | (3) |
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OBT of SC biquadratic filter |
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199 | (2) |
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Testing of high-order analogue filters |
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201 | (9) |
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Testing of high-order filters using bypassing |
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202 | (1) |
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Testing of high-order cascade filters using multiplexing |
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203 | (2) |
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Test of MLF OTA-C filters using multiplexing |
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205 | (2) |
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OBT structures for high-order OTA-C filters |
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207 | (3) |
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210 | (1) |
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210 | (3) |
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Test of A/D converters: From converter characteristics to built-in self-test proposals |
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213 | (22) |
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213 | (1) |
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214 | (6) |
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Static A/D converter performance parameters |
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216 | (2) |
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Dynamic A/D converter performance parameters |
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218 | (2) |
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A/D converter test approaches |
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220 | (8) |
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Set-up for A/D converter test |
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220 | (1) |
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Capturing the test response |
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221 | (1) |
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Static performance parameter test |
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222 | (4) |
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Dynamic performance parameter test |
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226 | (2) |
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A/D converter built-in self-test |
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228 | (3) |
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231 | (1) |
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232 | (3) |
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235 | (42) |
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235 | (1) |
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An overview of Σ Δ modulation: opening the ADC black box |
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236 | (7) |
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Principle of operation: Σ Δ modulation and noise shaping |
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236 | (2) |
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Digital filtering and decimation |
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238 | (1) |
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Σ Δ modulator architecture |
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239 | (4) |
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Characterization of Σ Δ Converters |
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243 | (11) |
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Congsequences of Σ Δ modulation for ADC characterization |
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243 | (1) |
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244 | (2) |
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246 | (2) |
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Applying a FFT with success |
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248 | (6) |
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254 | (5) |
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Limitations of the functional approach |
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255 | (1) |
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The built-in self-test approach |
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255 | (4) |
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259 | (12) |
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Model-based test concepts |
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259 | (3) |
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Polynomial model-based BIST |
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262 | (2) |
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Behavioural model-based BIST |
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264 | (7) |
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271 | (2) |
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273 | (4) |
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Phase-locked loop test methodologies: Current characterization and production test practices |
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277 | (32) |
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Introduction: Phase-locked loop operation and test motivations |
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277 | (10) |
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PLL key elements' operation and test issues |
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277 | (5) |
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Typical CP-PLL test specifications |
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282 | (5) |
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Traditional test techniques |
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287 | (14) |
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Characterization focused tests |
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287 | (11) |
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298 | (3) |
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301 | (5) |
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306 | (1) |
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306 | (3) |
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On-chip testing techniques for RF wireless transcelver system and components |
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309 | (38) |
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309 | (2) |
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Frequency-response test system for analogue baseband circuits |
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311 | (13) |
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311 | (2) |
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313 | (1) |
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Implementation as a complete on-chip test system with a digital interface |
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314 | (5) |
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Experimental evaluation of the FRCS |
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319 | (5) |
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CMOS amplitude detector for on-chip testing of RF circuits |
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324 | (9) |
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Gain and 1-dB compression point measurement with amplitude detectors |
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327 | (1) |
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CMOS RF amplitude detector design |
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328 | (2) |
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330 | (3) |
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Architecture for on-chip testing of wireless transceivers |
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333 | (9) |
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Switched loop-back architecture |
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333 | (4) |
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337 | (2) |
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339 | (3) |
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342 | (1) |
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343 | (4) |
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Tuning and calibration of analogue, mixed-signal and RF circuits |
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347 | (36) |
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347 | (1) |
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348 | (17) |
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Tuning system requirements for on-chip filters |
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348 | (1) |
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Frequency tuning and Q tuning |
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349 | (3) |
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Online and offline tuning |
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352 | (2) |
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354 | (1) |
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355 | (4) |
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359 | (1) |
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Tuning of high-order leapfrog filters |
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360 | (5) |
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Self-calibration techniques for PLL frequency synthesizers |
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365 | (6) |
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Need for calibration in PLL synthesizers |
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365 | (1) |
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PLL synthesizer with calibrated VCO |
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366 | (2) |
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Automatic PLL calibration |
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368 | (2) |
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Other PLL synthesizer calibration applications |
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370 | (1) |
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On-chip antenna impedance matching |
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371 | (7) |
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Requirement for on-chip antenna impedance matching |
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371 | (2) |
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373 | (3) |
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376 | (1) |
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377 | (1) |
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378 | (1) |
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378 | (5) |
Index |
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383 | |