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E-raamat: Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization

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  • Formaat: PDF+DRM
  • Ilmumisaeg: 17-May-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461435945
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Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and OptimizationSuurem pilt
  • Formaat: PDF+DRM
  • Ilmumisaeg: 17-May-2012
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461435945
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This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

This standalone reference surveys and compares mesh- and tree-based FPGA architectures. Comparing them via an exhaustive set of criteria, it displays the advantages of the tree-based hierarchical model, still largely unexplored despite its better performance.
1 Introduction
1(6)
1.1 Background
1(2)
1.2 Book Motivation and Contributions
3(3)
1.2.1 Exploration Environment for Heterogeneous Tree-Based FPGA Architectures
5(1)
1.2.1 Exploration of Tree-Based ASIF Architecture
5(1)
1.3 Book Organization
6(1)
2 FPGA Architectures: An Overview
7(42)
2.1 Introduction to FPGAs
8(1)
2.2 Programming Technologies
8(3)
2.2.1 SRAM-Based Programming Technology
9(1)
2.2.2 Flash Programming Technology
10(1)
2.2.3 Anti-fuse Programming Technology
10(1)
2.3 Configurable Logic Block
11(1)
2.4 FPGA Routing Architectures
12(12)
2.4.1 Island-Style Routing Architecture
14(5)
2.4.2 Hierarchical Routing Architecture
19(5)
2.5 Software Flow
24(15)
2.5.1 Logic Synthesis
25(1)
2.5.2 Technology Mapping
26(1)
2.5.3 Clustering/Packing
27(5)
2.5.4 Placement
32(4)
2.5.5 Routing
36(2)
2.5.6 Timing Analysis
38(1)
2.5.7 Bitstream Generation
39(1)
2.6 Research Trends in Reconfigurable Architectures
39(8)
2.6.1 Heterogeneous FPGA Architectures
40(3)
2.6.2 FPGAs to Structured Architectures
43(1)
2.6.3 Configurable ASIC Cores
44(1)
2.6.4 Processors Inside FPGAs
45(1)
2.6.5 Application Specific FPGAs
45(1)
2.6.6 Time-Multiplexed FPGAs
46(1)
2.6.7 Asynchronous FPGA Architecture
46(1)
2.7 Summary and Conclusion
47(2)
3 Homogeneous Architectures Exploration Environments
49(36)
3.1 Reference FPGA Architectures
50(10)
3.1.1 Mesh-Based FPGA Architecture
50(2)
3.1.2 Tree-Based FPGA Architecture
52(8)
3.1.3 Comparison with Mesh Model
60(1)
3.2 Architectures Exploration Environments
60(1)
3.3 Architecture Description
61(1)
3.3.1 Architecture Description of Tree-Based Architecture
61(1)
3.3.2 Architecture Description of Mesh-Based Architecture
61(1)
3.4 Software Flow
61(8)
3.4.1 Logic Optimization, Mapping and Packing
62(1)
3.4.2 Software Flow for Tree-Based Architecture
63(3)
3.4.3 Software Flow for Mesh-Based Architecture
66(1)
3.4.4 Timing Analysis
66(1)
3.4.5 Area and Delay Models
67(2)
3.5 Experimentation and Analysis
69(8)
3.5.1 Architectures Optimization Approaches
69(4)
3.5.2 Effect of LUT and Arity Size on Tree-Based FPGA Architecture
73(2)
3.5.3 Comparison Between Homogeneous Mesh and Tree-Based FPGAs
75(2)
3.6 FPGA Hardware Generation
77(7)
3.6.1 FPGA Generation Flow
81(1)
3.6.2 FPGA VHDL Model Generation
82(1)
3.6.3 FPGA Layout Generation
83(1)
3.7 Summary and Conclusion
84(1)
4 Heterogeneous Architectures Exploration Environments
85(38)
4.1 Introduction and Previous Work
85(2)
4.2 Reference Heterogeneous FPGA Architectures
87(5)
4.2.1 Heterogeneous Tree-Based FPGA Architecture
87(3)
4.2.2 Heterogeneous Mesh-Based FPGA Architecture
90(2)
4.3 Architecture Description
92(4)
4.3.1 Architecture Description of Heterogeneous Tree-Based Architecture
92(3)
4.3.2 Architecture Description of Heterogeneous Mesh-Based Architecture
95(1)
4.4 Software Flow
96(7)
4.4.1 Parsers
97(3)
4.4.2 Software Flow for Heterogeneous Tree-Based Architecture
100(1)
4.4.3 Software Flow for Heterogeneous Mesh-Based Architecture
101(2)
4.4.4 Area Model
103(1)
4.5 Exploration Techniques
103(5)
4.5.1 Exploration Techniques for Heterogeneous Tree-Based Architecture
104(2)
4.5.2 Exploration Techniques for Heterogeneous Mesh-Based Architecture
106(2)
4.6 Experimentation and Analysis
108(13)
4.6.1 Benchmark Selection
108(2)
4.6.2 Experimental Methodology
110(1)
4.6.3 Results Using Individual Experimentation Approach
111(6)
4.6.4 Results Using Generalized Experimentation Approach
117(4)
4.7 Heterogeneous FPGA Hardware Generation
121(1)
4.8 Summary and Conclusion
122(1)
5 Tree-Based Application Specific Inflexible FPGA
123(30)
5.1 Introduction and Previous Work
123(2)
5.2 Reference FPGA Architectures
125(1)
5.2.1 Reference Tree-Based FPGA Architecture
125(1)
5.2.2 Reference Mesh-Based FPGA Architecture
125(1)
5.3 Software Flow
126(1)
5.4 ASIF Generation Techniques
126(6)
5.4.1 ASIF-Normal Partitioning/Placement Normal Routing
127(1)
5.4.2 ASIF-Efficient Partitioning/Placement Normal Routing
128(2)
5.4.3 ASIF-Normal Partitioning/Placement Efficient Routing
130(2)
5.4.4 ASIF-Efficient Partitioning/Placement Efficient Routing
132(1)
5.5 ASIF Area Model
132(1)
5.6 Experimental Results and Analysis
133(14)
5.6.1 Effect of Different ASIF Generation Techniques on Tree-Based Architecture
133(5)
5.6.2 Effect of LUT and Arity Size on Tree-Based ASIF
138(4)
5.6.3 Comparison Between Mesh-Based and Tree-Based ASIFs
142(2)
5.6.4 Quality Analysis of Tree-Based ASIF
144(2)
5.6.5 Quality Comparison Between Mesh-Based and Tree-Based ASIFs
146(1)
5.7 ASIF Hardware Generation
147(3)
5.7.1 ASIF Generation Flow
147(1)
5.7.2 ASIF VHDL Model Generation
147(3)
5.7.3 ASIF Layout Generation
150(1)
5.8 Summary and Conclusion
150(3)
6 Tree-Based ASIF Using Heterogeneous Blocks
153(20)
6.1 Reference Heterogeneous FPGA Architectures
153(2)
6.1.1 Heterogeneous Tree-Based FPGA Architecture
154(1)
6.1.2 Heterogeneous Mesh-Based FPGA Architecture
154(1)
6.1.3 Software Flow
155(1)
6.2 Heterogeneous ASIF Generation Techniques
155(1)
6.3 Experimentation and Analysis
156(10)
6.3.1 Experimental Benchmarks
156(1)
6.3.2 Effect of Different ASIF Generation Techniques on Heterogeneous Tree-Based ASIF
157(4)
6.3.3 Effect of LUT and Arity Size on Heterogeneous Tree-Based ASIF
161(3)
6.3.4 Comparison Between Heterogeneous Mesh-Based and Tree-Based ASIFs
164(2)
6.4 Quality Analysis of Heterogeneous Tree-Based ASIF
166(2)
6.4.1 Quality Comparison Between Heterogeneous Mesh-Based and Tree-Based ASIF
168(1)
6.5 Heterogeneous ASIF Hardware Generation
168(3)
6.6 Summary and Conclusion
171(2)
7 Conclusion and Future Lines of Research
173(8)
7.1 Summary of Contributions
173(4)
7.1.1 Heterogeneous Tree-Based FPGA Exploration Environment
174(1)
7.1.2 Tree-Based ASIF Exploration
174(2)
7.1.3 FPGA and ASIF Hardware Generation for Tree-Based Architecture
176(1)
7.2 Suggestions for Future Research
177(4)
7.2.1 Datapath Oriented FPGA Architectures
177(1)
7.2.2 Timing Analysis
178(1)
7.2.3 Integrating ASIF Blocks in an FPGA Architecture
179(1)
7.2.4 Further Optimizing the ASIF Generation
179(1)
7.2.5 The Unexplored Parameters of Mesh-Based Architecture
180(1)
References 181
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