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E-raamat: Tunnel Field-effect Transistors (TFET): Modelling and Simulation

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  • Formaat: EPUB+DRM
  • Ilmumisaeg: 27-Sep-2016
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9781119246305
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Tunnel Field-effect Transistors (TFET): Modelling and SimulationSuurem pilt
  • Formaat: EPUB+DRM
  • Ilmumisaeg: 27-Sep-2016
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9781119246305
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Research into Tunneling Field Effect Transistors (TFETs) has developed significantly in recent times, indicating their significance in low power integrated circuits. This book describes the qualitative and quantitative fundamental concepts of TFET functioning, the essential components of the problem of modelling the TFET, and outlines the most commonly used mathematical approaches for the same in a lucid language.

 

Divided into eight chapters, the topics covered include: Quantum Mechanics, Basics of Tunneling, The Tunnel FET, Drain current modelling of Tunnel FET: The task and its challenges, Modeling the Surface Potential in TFETs, Modelling the Drain Current, and Device simulation using Technology Computer Aided Design (TCAD). The information is well organized, describing different phenomena in the TFETs using simple and logical explanations.

 

Key features:

 

               * Enables readers to understand the basic concepts of TFET functioning and modelling in order to read, understand, and critically analyse current research on the topic with ease.

 

               * Includes state-of-the-art work on TFETs, attempting to cover all the recent research articles published on the subject.

 

               * Discusses the basic physics behind tunneling, as well as the device physics of the TFETs.

 

               * Provides detailed discussion on device simulations along with device physics so as to enable researchers to carry forward their study on TFETs.

 

 

Primarily targeted at new and practicing researchers and post graduate students, the book would particularly be useful for researchers who are working in the area of compact and analytical modelling of semiconductor devices.

Preface viii
1 Quantum mechanics
1(17)
1.1 Introduction to quantum mechanics
1(12)
1.1.1 The double slit experiment
1(3)
1.1.2 Basic concepts of quantum mechanics
4(6)
1.1.3 Schrodinger's equation
10(3)
1.2 Basic quantum physics problems
13(5)
1.2.1 Free particle
13(1)
1.2.2 Particle in a one-dimensional box
14(3)
Reference
17(1)
2 Basics of tunnelling
18(21)
2.1 Understanding tunnelling
18(5)
2.1.1 Qualitative description
18(2)
2.1.2 Rectangular barrier
20(3)
2.2 WKB approximation
23(3)
2.3 Landauer's tunnelling formula
26(3)
2.4 Advanced tunnelling models
29(10)
2.4.1 Non-local tunnelling models
30(1)
2.4.2 Local tunnelling models
30(8)
References
38(1)
3 The tunnel FET
39(39)
3.1 Device structure
39(3)
3.1.1 The need for tunnel FETs
39(2)
3.1.2 Basic TFET structure
41(1)
3.2 Qualitative behaviour
42(21)
3.2.1 Band diagram
42(10)
3.2.2 Device characteristics
52(7)
3.2.3 Performance dependence on device parameters
59(4)
3.3 Types of TFETs
63(11)
3.3.1 Planar TFETs
63(7)
3.3.2 Three-dimensional TFETs
70(2)
3.3.3 Carbon nanotube and graphene TFETs
72(1)
3.3.4 Point versus line tunnelling in TFETs
73(1)
3.4 Other steep subthreshold transistors
74(4)
References
74(4)
4 Drain current modelling of tunnel FET: the task and its challenges
78(12)
4.1 Introduction
78(3)
4.2 TFET modelling approach
81(6)
4.2.1 Finding the value of ψC
82(1)
4.2.2 Modelling the surface potential in the source--channel junction
83(2)
4.2.3 Finding the tunnelling current
85(2)
4.3 MOSFET modelling approach
87(3)
References
89(1)
5 Modelling the surface potential in TFETs
90(50)
5.1 The pseudo-2D method
91(7)
5.1.1 Parabolic approximation of potential distribution
91(3)
5.1.2 Solving the 2D Poisson equation using parabolic approximation
94(1)
5.1.3 Solution for the surface potential
95(3)
5.2 The variational approach
98(9)
5.2.1 The variational form of Poisson's equation
99(2)
5.2.2 Solution of the variational form of Poisson's equation in a TFET
101(6)
5.3 The infinite series solution
107(12)
5.3.1 Solving the 2D Poisson equation using separation of variables
107(2)
5.3.2 Solution of the homogeneous boundary value problem
109(3)
5.3.3 The solution to the 2D Poisson equation in a TFET
112(2)
5.3.4 The infinite series solution to Poisson's equation in a TFET
114(5)
5.4 Extension of surface potential models to different TFET structures
119(12)
5.4.1 DG TFET
119(3)
5.4.2 GAA TFET
122(3)
5.4.3 Dual material gate TFET
125(6)
5.5 The effect of localised charges on the surface potential
131(1)
5.6 Surface potential in the depletion regions
132(3)
5.7 Use of smoothing functions in the surface potential models
135(5)
References
137(3)
6 Modelling the drain current
140(23)
6.1 Non-local methods
142(5)
6.1.1 Landauer's tunnelling formula in TFETs
142(1)
6.1.2 WKB approximation in TFETs
143(1)
6.1.3 Obtaining the drain current
144(3)
6.2 Local methods
147(10)
6.2.1 Numerical integration
148(1)
6.2.2 Shortest tunnelling length
148(2)
6.2.3 Constant polynomial term assumption
150(2)
6.2.4 Tangent line approximation
152(5)
6.3 Threshold voltage models
157(6)
6.3.1 Constant current method
158(1)
6.3.2 Constant tunnelling length
159(1)
6.3.3 Transconductance change (TC) method
160(1)
References
161(2)
7 Device simulation using ATLAS
163(18)
7.1 Simulations using ATLAS
164(7)
7.1.1 Inputs and outputs
165(1)
7.1.2 Structure specification
166(3)
7.1.3 Material parameters and model specification
169(1)
7.1.4 Numerical method specification
170(1)
7.1.5 Solution specification
170(1)
7.2 Analysis of simulation results
171(3)
7.3 SOI MOSFET example
174(7)
Reference
180(1)
8 Simulation of TFETs
181(13)
8.1 SOI TFET
181(7)
8.2 Other tunnelling models
188(2)
8.2.1 Schenk band-to-band tunnelling model
188(1)
8.2.2 Non-local band-to-band tunnelling
188(2)
8.3 Gate all around nanowire TFET
190(4)
References
193(1)
Index 194
Dr. M. Jagadesh Kumar obtained his MS in Electrical Engineering (EE) and PhD in EE from the Indian Institute of Technology (IIT), Madras. He is currently the NXP (Philips) Chair Professor at IIT Delhi by Philips Semiconductors, Netherlands (now NXP Semiconductors India Pvt Ltd). He works in the area of Nanoelectronic Devices, Nanoscale Device modeling and simulation, Innovative Device Design and Power semiconductor devices. He has published extensively in the above areas with four book chapters and more than 200 publications in refereed journals and conference proceedings including 70 IEEE Journal papers. Six patent applications have been filed based on his research.

Rajat Vishnoi received his B.Tech degree in EE from the Indian Institute of Technology (IIT), Kanpur, in 2012. He is currently pursuing his Ph.D. degree in Electrical Engineering at the Indian Institute of Technology, Delhi. His research interests include semiconductor device modelling, design and fabrication.





Pratyush Pandey completed his undergraduate in Electrical Engineering from the Indian Institute of Technology (IIT), Kanpur, in 2011. In 2007 he received a Silver Medal in the International Physics Olympiad, and a Gold Medal in the Indian National Chemistry Olympiad. During his undergraduate studies, he worked on quantum error correction codes, quantum cryptography, and applied information theory. Subsequently, he worked as a Research Assistant at IIT Delhi on the analytical modelling of TFETs. He has developed analytical models for Double Gate, Dual Material Gate, and Nanowire TFETs. He is currently a graduate student advised by Dr. Alan Seabaugh at Notre Dame, where he is involved in the simulation, modelling, characterisation, and fabrication of TMD TFETs. He is also a reviewer for IEEE Transactions on Electron Devices, and the Journal of Computational Electronics.
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