|
|
1 | (18) |
|
1.1 Supply Voltage Reduction: A Brief History |
|
|
1 | (2) |
|
1.2 Reducing the Energy Consumption |
|
|
3 | (5) |
|
|
4 | (1) |
|
1.2.2 Minimizing the Energy Consumption |
|
|
5 | (2) |
|
1.2.3 Energy-Delay Product |
|
|
7 | (1) |
|
1.3 Ultra-Low-Voltage Digital Design |
|
|
8 | (2) |
|
|
10 | (1) |
|
1.5 Current State-of-the-Art in Literature |
|
|
10 | (5) |
|
|
15 | (4) |
|
|
17 | (2) |
|
2 Sub-Threshold Operation: Theory and Challenges |
|
|
19 | (28) |
|
|
20 | (9) |
|
2.1.1 Different Operating Regions |
|
|
21 | (3) |
|
|
24 | (4) |
|
|
28 | (1) |
|
2.2 Challenges of Sub-Threshold Operation |
|
|
29 | (6) |
|
|
29 | (1) |
|
|
30 | (1) |
|
|
31 | (3) |
|
|
34 | (1) |
|
|
35 | (7) |
|
|
36 | (4) |
|
|
40 | (1) |
|
|
41 | (1) |
|
|
42 | (1) |
|
|
43 | (4) |
|
|
43 | (4) |
|
3 Gate-Level Building Blocks |
|
|
47 | (38) |
|
3.1 Circuit Topology Comparison |
|
|
48 | (27) |
|
3.1.1 Standard CMOS Logic |
|
|
48 | (12) |
|
|
60 | (2) |
|
3.1.3 Pass Transistor Logic |
|
|
62 | (2) |
|
3.1.4 Transmission Gate Logic |
|
|
64 | (7) |
|
|
71 | (4) |
|
3.2 Chosen Circuit Topologies |
|
|
75 | (2) |
|
|
75 | (1) |
|
|
76 | (1) |
|
|
77 | (3) |
|
|
78 | (2) |
|
|
80 | (1) |
|
3.4 Sizing in Different Prototypes |
|
|
80 | (1) |
|
|
80 | (5) |
|
|
81 | (4) |
|
|
85 | (28) |
|
4.1 Theoretical Considerations |
|
|
86 | (6) |
|
|
87 | (1) |
|
4.1.2 Total Energy Consumption |
|
|
88 | (4) |
|
4.2 Cascading Logic Gates |
|
|
92 | (6) |
|
|
92 | (2) |
|
|
94 | (2) |
|
4.2.3 Differential TG Logic |
|
|
96 | (2) |
|
|
98 | (1) |
|
|
98 | (9) |
|
|
98 | (1) |
|
4.3.2 Benefits and Drawbacks |
|
|
99 | (1) |
|
|
100 | (5) |
|
4.3.4 Design Considerations |
|
|
105 | (2) |
|
|
107 | (2) |
|
|
107 | (1) |
|
|
108 | (1) |
|
|
109 | (2) |
|
|
111 | (2) |
|
|
112 | (1) |
|
|
113 | (28) |
|
|
114 | (6) |
|
|
114 | (1) |
|
|
114 | (1) |
|
5.1.3 Ultra-Low-Voltage Design |
|
|
114 | (3) |
|
5.1.4 Measurement Results |
|
|
117 | (2) |
|
5.1.5 State-of-the-Art Comparison |
|
|
119 | (1) |
|
|
120 | (1) |
|
5.2 Multiply-Accumulate Unit |
|
|
120 | (18) |
|
|
120 | (1) |
|
|
121 | (2) |
|
5.2.3 Ultra-Low-Voltage Design |
|
|
123 | (7) |
|
5.2.4 Measurement Results |
|
|
130 | (6) |
|
5.2.5 State-of-the-Art Comparison |
|
|
136 | (1) |
|
|
137 | (1) |
|
|
138 | (3) |
|
|
138 | (3) |
|
|
141 | (30) |
|
|
142 | (1) |
|
6.2 JPEG Encoding Algorithm |
|
|
142 | (2) |
|
6.3 Ultra-Low-Voltage Design |
|
|
144 | (1) |
|
|
144 | (15) |
|
|
144 | (2) |
|
|
146 | (2) |
|
|
148 | (1) |
|
6.4.4 Zigzag Matrix and Huffman Encoder |
|
|
149 | (7) |
|
|
156 | (3) |
|
|
159 | (2) |
|
6.6 State-of-the-Art Comparison |
|
|
161 | (4) |
|
6.7 Lookup Table Improvements |
|
|
165 | (4) |
|
|
169 | (2) |
|
|
169 | (2) |
|
|
171 | (10) |
|
|
171 | (3) |
|
7.2 State-of-the-Art Comparison |
|
|
174 | (3) |
|
|
177 | (1) |
|
7.4 Suggestions for Future Work |
|
|
178 | (3) |
|
7.4.1 Energy-Efficient SRAM |
|
|
179 | (1) |
|
|
179 | (1) |
|
7.4.3 Standard Digital Design Flow |
|
|
179 | (1) |
|
7.4.4 Inter-Die Variations |
|
|
180 | (1) |
|
7.4.5 Temperature-Dependence |
|
|
180 | (1) |
|
7.4.6 Efficient DC-DC Converter |
|
|
180 | (1) |
|
|
180 | (1) |
|
A Current State-of-the-Art in Literature |
|
|
181 | (8) |
|
|
184 | (5) |
Index |
|
189 | |