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E-raamat: Variation-Aware Advanced CMOS Devices and SRAM

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Variation-Aware Advanced CMOS Devices and SRAMSuurem pilt
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This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM.

The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reader with a deep understanding of the major random variation sources, and the characterization of each random variation source. Furthermore, the book presents various CMOS device designs to surmount the random variation in future CMOS technology, emphasizing the applications to SRAM.

1 Introduction: Barriers Preventing CMOS Device Technology from Moving Forward
1(18)
1.1 Introduction
1(2)
1.2 Overview of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
3(9)
1.2.1 Energy Crisis in MOSFET
3(5)
1.2.2 Thin Body MOSFETs Allow CMOS Technology to Move Forward Aggressively
8(1)
1.2.3 A New Class of Switch Enables CMOS Technology to Move Forward
9(3)
1.3 Process-Induced Variation
12(3)
1.3.1 Process-Induced Systematic Variation
13(1)
1.3.2 Process-Induced Random Variation
13(2)
References
15(4)
Part I Understanding of Process-Induced Random Variation
2 Line Edge Roughness (LER)
19(18)
2.1 Introduction
19(1)
2.2 Physical Origin of Line Edge Roughness
20(4)
2.2.1 LER of Mask Patterns
21(1)
2.2.2 Variations in the Dose of Light Exposure
21(1)
2.2.3 LER Generation in Chemically Amplified (CA) Resists
22(1)
2.2.4 Intrinsic Roughness of the Resist
23(1)
2.3 Characterization of Line Edge Roughness
24(5)
2.3.1 Line Edge Roughness (LER)
24(3)
2.3.2 Line Width Roughness (LWR)
27(2)
2.4 Impact of Double Patterning on Line Edge Roughness
29(3)
2.4.1 Double Pattern and Double Etching
29(2)
2.4.2 Self-aligned Double Patterning
31(1)
References
32(5)
3 Random Dopant Fluctuation (RDF)
37(16)
3.1 Introduction
37(2)
3.2 Physical Origin of Random Dopant Fluctuation
39(4)
3.2.1 Ion Implantation Step
39(1)
3.2.2 Annealing Step for Repairing Damage and Activating Impurities
40(3)
3.3 Characterization of Random Dopant Fluctuation (RDF)
43(8)
3.3.1 Kinetic Monte Carlo (KMC) Simulation
44(3)
3.3.2 Analytical Model
47(4)
References
51(2)
4 Work Function Variation (WFV)
53(18)
4.1 Introduction
53(2)
4.2 The Physical Origins of WFV
55(4)
4.2.1 Characteristics of Metal Grains
55(1)
4.2.2 Dependence of the Metal Work Function on the Grain Orientation
56(2)
4.2.3 Impact of WFV on VTH Variation
58(1)
4.3 Characterization of WFV
59(6)
4.3.1 Statistical Analysis
59(2)
4.3.2 Ratio of Average Grain Size to Gate Area (RGG)
61(4)
References
65(6)
Part II Variation-Aware Advanced CMOS Devices
5 Tri-Gate Mosfet
71(20)
5.1 Introduction
71(1)
5.2 RDF in Tri-Gate Mosfet
72(5)
5.3 LER in Tri-Gate Mosfet
77(4)
5.4 WFV in Tri-Gate Mosfet
81(7)
References
88(3)
6 Quasi-Planar Trigate (QPT) Bulk Mosfet
91(12)
6.1 QPT Bulk Mosfet
91(1)
6.2 Fabrication of a QPT Bulk Mosfet
92(1)
6.3 Results and Discussion
93(6)
6.3.1 Improved Performance in QPT Bulk Mosfet (Vs. Conventional Mosfet)
93(2)
6.3.2 Suppressed VT Variation by the QPT Structure
95(1)
6.3.3 Improved Short Channel Effect in the QPT Bulk Mosfet
96(1)
6.3.4 Increased Narrow Width Effect in the QPT Bulk Mosfet
97(1)
6.3.5 A Compact Model for the QPT Bulk Mosfet
98(1)
6.4 Benefits of the Quasi-Planar Bulk CMOS Technology for 6T-SRAM
99(1)
6.4.1 Yield Enhancement in the QPT-Based 6-T SRAM Bit Cells
99(1)
6.4.2 Scaling of the Power Supply Voltage (VDD)
99(1)
References
100(3)
7 Tunnel FET (TFET)
103(20)
7.1 Introduction
103(2)
7.2 Random Dopant Fluctuation (RDF) in TFET
105(4)
7.3 Line Edge Roughness (LER) in TFET
109(4)
7.4 Work-Function Variation (WFV) in TFET
113(6)
References
119(4)
Part III Static Random Access Memory (SRAM) Based on Advanced CMOS Devices
8 Applications in Static Random Access Memory (SRAM)
123
8.1 Introduction
123(1)
8.2 The Operating Principle of SRAM
124(6)
8.2.1 Read Operation
125(3)
8.2.2 Write Operation
128(2)
8.3 Metrics for SRAM Read/Write Noise Margin
130(6)
8.3.1 Conventional Metrics for SRAM Read/Write Operation
131(2)
8.3.2 Large-Scale Metrics for SRAM Read/Write Operation
133(3)
8.4 SRAM Yield Estimation Techniques
136(3)
8.4.1 Compact Model for Mosfet
136(1)
8.4.2 Standard Monte Carlo Simulation
137(1)
8.4.3 Worst Case Sampling Method
138(1)
References
139
Prof. Changhwan Shin is an Assistant Professor in School of Electrical and Computer Engineering in University of Seoul. Prof. Shin is a graduate of Korea University (BE) and University of California Berkeley (Ph.D). Also, he is Technical Committee Members for IEEE SOI Conference and European Solid-State Device Research Conference (ESSDERC). His research activities cover Electronic Devices and Integrated Circuits; Advanced electronic device architecture for various types of System-on-Chip(SoC) memory and logic devices/ All-in-one Variability Analysis for Nanometer-scale Electronic Devices/ Post-Silicon Technology (CNT, Graphene) & Bio-applications/ Device-and-Circuit Co-optimization: "Low-Level" Digital/Analog Circuit Design Methodology Development/ Programmable Chip Development using Advanced Electronic Devices.
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