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E-raamat: Variation-Aware Analog Structural Synthesis: A Computational Intelligence Approach

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This book describes new tools for front end analog designers, starting with global variation-aware sizing, and extending to novel variation-aware topology design. The tools aid design through automation, but more importantly, they also aid designer insight through automation. We now describe four design tasks, each more general than the previous, and how this book contributes design aids and insight aids to each. The ?rst designer task targeted is global robust sizing. This task is supported by a design tool that does automated, globally reliable, variation-aware s- ing (SANGRIA),and an insight-aiding tool that extracts designer-interpretable whitebox models that relate sizings to circuit performance (CAFFEINE). SANGRIA searches on several levels of problem dif culty simultaneously, from lower cheap-to-evaluate exploration layers to higher full-evaluation exploitation layers (structural homotopy). SANGRIAmakes maximal use of circuit simulations by performing scalable data mining on simulation results to choose new candidate designs. CAFFEINE accomplishes its task by tre- ing function induction as a tree-search problem. It constrains its tree search space via a canonical-functional-form grammar, and searches the space with grammatically constrained genetic programming. The second designer task is topology selection/topology design. Topology selection tools must consider a broad variety of topologies such that an app- priate topology is selected, must easily adapt to new semiconductor process nodes, and readily incorporate new topologies. Topology design tools must allow designers to creatively explore new topology ideas as rapidly as possible.

Arvustused

From the reviews:

This book is squarely aimed at analog circuit designers who are searching for new approaches to analog structural design and optimization. Those most likely to benefit from this book are experts in the field of industrial circuit design seeking insight into new design tools. for the non-expert, with only a cursory understanding of the background material, the processes and results described in this book are an inspiring example of real-world applications of evolutionary design. (John Rieffel, Genetic Programming and Evolvable Machines, Vol. 12, 2011)

Preface xi
Acronyms and Notation xv
Introduction
1(26)
Motivation
1(3)
Background and Contributions to Analog CAD
4(13)
Background and Contributions to AI
17(7)
Analog CAD Is a Fruitfly for AI
24(1)
Conclusion
24(3)
Variation-Aware Sizing: Background
27(20)
Introduction and Problem Formulation
27(5)
Review of Yield Optimization Approaches
32(12)
Conclusion
44(3)
Globally Reliable, Variation-Aware Sizing: SANGRIA
47(38)
Introduction
47(1)
Foundations: Model-Building Optimization (MBO)
48(5)
Foundations: Stochastic Gradient Boosting
53(6)
Foundations: Homotopy
59(1)
Sangria Algorithm
59(11)
Sangria Experimental Results
70(12)
On Scaling to Larger Circuits
82(1)
Conclusion
83(2)
Knowledge Extraction in Sizing: Caffeine
85(58)
Introduction and Problem Formulation
85(5)
Background: GP and Symbolic Regression
90(4)
Caffeine Canonical Form Functions
94(2)
Caffeine Search Algorithm
96(6)
Caffeine Results
102(11)
Scaling Up Caffeine: Algorithm
113(4)
Scaling Up Caffeine: Results
117(4)
Application: Behaviorial Modeling
121(4)
Application: Process-Variable Robustness Modeling
125(13)
Application: Design-Variable Robustness Modeling
138(1)
Application: Automated Sizing
139(1)
Application: Analytical Performance Tradeoffs
139(1)
Sensitivity To Search Algorithm
139(1)
Conclusion
140(3)
Circuit Topology Synthesis: Background
143(26)
Introduction
143(2)
Topology-Centric Flows
145(8)
Reconciling System-Level Design
153(3)
Requirements for a Topology Selection/Design Tool
156(1)
Open-Ended Synthesis and the Analog Problem Domain
157(10)
Conclusion
167(2)
Trustworthy Topology Synthesis: MOJITO Search Space
169(22)
Introduction
169(4)
Search Space Framework
173(7)
A Highly Searchable Op Amp Library
180(1)
Operating-Point Driven Formulation
181(1)
Worked Example
182(4)
Size of Search Space
186(4)
Conclusion
190(1)
Trustworthy Topology Synthesis: MOJITO Algorithm
191(24)
Introduction
191(2)
High-Level Algorithm
193(3)
Search Operators
196(3)
Handling Multiple Objectives
199(3)
Generation of Initial Individuals
202(5)
Experimental Setup
207(1)
Experiment: Hit Target Topologies?
208(1)
Experiment: Diversity?
209(1)
Experiment: Human-Competitive Results?
209(3)
Discussion: Comparison to Open-Ended Structural Synthesis
212(1)
Conclusion
213(2)
Knowledge Extraction in Topology Synthesis
215(16)
Introduction
215(3)
Generation of Database
218(1)
Extraction of Specs-To-Topology Decision Tree
219(4)
Global Nonlinear Sensitivity Analysis
223(4)
Extraction of Analytical Performance Tradeoffs
227(2)
Conclusion
229(2)
Variation-Aware Topology Synthesis & Knowledge Extraction
231(16)
Introduction
231(1)
Problem Specification
231(1)
Background
232(2)
Towards a Solution
234(1)
Proposed Approach: MOJITO-R
234(3)
MOJITO-R Experimental Validation
237(7)
Conclusion
244(3)
Novel Variation-Aware Topology Synthesis
247(20)
Introduction
247(1)
Background
248(1)
MOJITO-N Algorithm and Results
249(4)
ISCLEs Algorithm And Results
253(13)
Conclusion
266(1)
Conclusion
267(10)
General Contributions
267(1)
Specific Contributions
267(3)
Future Work
270(5)
Final Remarks
275(2)
References 277(24)
Index 301
Trent McConaghy is co-founder and Chief Scientific Officer of Solido Design Automation Inc. He was a co-founder and Chief Scientist of Analog Design Automation Inc., which was acquired by Synopsys Inc. in 2004. Prior to that, he did research for the Canadian Department of National Defense. He received his PhD degree in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 2008. He received a Bachelors in Engineering (with great distinction), and a Bachelors in Computer Science (with great distinction), both from the University of Saskatchewan, Canada, in 1999. He has about 40 peer-reviewed technical papers and patents granted / pending. He has given invited talks / tutorials at many labs, universities, and conferences such as JPL, MIT, ICCAD, and DAC. He is regularly a technical program committee member and reviewer in both the CAD and intelligent systems fields, such as IEEE Trans CAD, ACM TODAES, Electronics Letters, to IEEE Trans Evolutionary Computation, the Journal of Genetic Programming and Evolvable Machines, GPTP, GECCO, ICES, etc. His research interest is in statistical machine learning and intelligent systems, with transistor-level CAD applications such as variation-aware design, analog topology design, automated sizing, knowledge extraction, and symbolic modeling.

Michiel Steyaert was born in Aalst, Belgium, in 1959. He received the masters degree in electrical-mechanical engineering and the Ph.D. degree in electronics from the Katholieke Universiteit Leuven (K.U.Leuven), Heverlee, Belgium in 1983 and 1987, respectively. From 1983 to 1986 he obtained an IWNOL fellowship (Belgian National Fundation for Industrial Research) which allowed him to work as a Research Assistant  at the Laboratory ESAT at K.U.Leuven. In 1987 he was responsible for several industrial projects in the field of analog micropower circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988 he was a Visiting Assistant Professor atthe University of California, Los Angeles. In 1989 he was appointed by the National Fund of Scientific Research (Belgium) as Research Associate, in 1992 as a Senior Research Associate and in 1996 as a Research Director at the Laboratory ESAT, K.U.Leuven. Between 1989 and 1996 he was also a part-time Associate Professor. He is now a Full Professor at the K.U.Leuven. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Prof.Steyaert received the 1990 and 2001 European Solid-State Circuits Conference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications. Prof.Steyaert received the 1995 and 1997 IEEE-ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and is currently an IEEE-Fellow.

Georges Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. He currently is a Full Professor at the Katholieke Universiteit Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area, including several European projects (EU, MEDEA, ESA). He has authored or coauthored five books and more than 300 papers in edited books, international journals and conference proceedings. He regularly is a member of the Program Committees of international conferences (DAC, ICCAD, ISCAS, DATE, CICC...), and served as General Chair of the DATE conference in 2006 and of the International Conference on Computer-Aided Design in 2007. He serves regularly as member of editorial boards of international journals (IEEE Transactions on Circuits and Systems, Springer international journal on Analog Integrated Circuits and Signal Processing, Elsevier Integration). He received the 1995 Best Paper Award in the John Wiley international journal on Circuit Theory and Applications, and was the 1997 Laureate of the Belgian Royal Academy on Sciences, Literature and Arts in the discipline of Engineering. He received the 2000 Alcatel Award from the Belgian National Fund of Scientific Research for his innovative research in telecommunications, and won the DATE 2004 Best Paper Award. He is a Fellow of the IEEE, served as elected member of the Board of Governors of the IEEE Circuits And Systems (CAS) society and as chairman of the IEEE Benelux CAS chapter. He served as the President of the IEEE Circuits And Systems (CAS) Society in 2005. He was elected DATE Fellow in 2007, and received the IEEE Computer Society Outstanding Contribution Award and the IEEE Circuits and Systems Society Meritorious Service Award in 2007.