Preface |
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xi | |
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xv | |
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xvii | |
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1 | (6) |
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1.1 The VHDL Design Cycle |
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1 | (1) |
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2 | (1) |
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1.3 The Standardisation Process |
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3 | (1) |
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1.4 Unification of VHDL Standards |
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4 | (1) |
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4 | (3) |
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2 Register-Transfer Level Design |
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7 | (12) |
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2.1 The RTL Design Stages |
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8 | (1) |
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8 | (2) |
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2.3 Identify the Data Operations |
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10 | (2) |
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2.4 Determine the Data Precision |
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12 | (1) |
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2.5 Choose Resources to Provide |
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12 | (1) |
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2.6 Allocate Operations to Resources |
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13 | (1) |
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2.7 Design the Controller |
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14 | (1) |
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2.8 Design the Reset Mechanism |
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15 | (1) |
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2.9 VHDL Description of the RTL Design |
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15 | (1) |
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16 | (3) |
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19 | (18) |
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19 | (1) |
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3.2 Entities and Architectures |
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20 | (2) |
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22 | (3) |
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25 | (2) |
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27 | (2) |
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29 | (1) |
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3.7 Simple Signal Assignments |
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30 | (1) |
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3.8 Conditional Signal Assignments |
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31 | (2) |
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3.9 Selected Signal Assignment |
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33 | (1) |
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34 | (3) |
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37 | (26) |
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37 | (1) |
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37 | (1) |
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38 | (1) |
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39 | (1) |
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39 | (2) |
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41 | (5) |
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46 | (1) |
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4.8 Multi-Valued Logic Types |
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47 | (1) |
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48 | (1) |
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49 | (4) |
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4.11 Aggregates, Strings and Bit-Strings |
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53 | (3) |
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56 | (4) |
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4.13 More on Selected Signal Assignments |
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60 | (3) |
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63 | (22) |
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5.1 The Standard Operators |
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63 | (1) |
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64 | (6) |
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70 | (3) |
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73 | (3) |
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76 | (3) |
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79 | (5) |
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5.7 Concatenation Operator |
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84 | (1) |
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85 | (66) |
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6.1 Synthesis Type System |
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85 | (2) |
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6.2 Making the Packages Visible |
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87 | (3) |
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6.3 Logic Types-Std_Logic_1164 |
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90 | (5) |
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6.4 Numeric Types - Numeric_Std |
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95 | (10) |
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6.5 Fixed-Point Types - Fixed_Pkg |
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105 | (14) |
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6.6 Floating-Point Types - Float_Pkg |
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119 | (15) |
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134 | (10) |
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144 | (2) |
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6.9 Mixing Types in Expressions |
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146 | (1) |
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147 | (4) |
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151 | (16) |
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7.1 The Std_Logic_Arith Package |
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151 | (1) |
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7.2 Contents of Std_Logic_Arith |
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152 | (9) |
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161 | (1) |
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162 | (2) |
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7.5 Mixing Types in Expressions |
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164 | (3) |
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167 | (24) |
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167 | (3) |
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170 | (1) |
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171 | (1) |
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172 | (5) |
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177 | (1) |
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178 | (3) |
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181 | (6) |
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187 | (4) |
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191 | (22) |
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9.1 Basic D-Type Register |
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191 | (1) |
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192 | (1) |
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193 | (2) |
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195 | (4) |
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199 | (1) |
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199 | (1) |
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200 | (1) |
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201 | (2) |
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203 | (5) |
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208 | (2) |
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9.11 Registered Variables |
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210 | (1) |
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211 | (2) |
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213 | (30) |
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10.1 The Role of Components |
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213 | (1) |
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214 | (5) |
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219 | (1) |
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220 | (2) |
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10.5 Parameterised Components |
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222 | (3) |
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225 | (5) |
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230 | (13) |
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243 | (36) |
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11.1 The Role of Subprograms |
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243 | (1) |
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243 | (11) |
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254 | (4) |
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258 | (3) |
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261 | (6) |
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11.6 Declaring Subprograms |
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267 | (3) |
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270 | (9) |
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279 | (22) |
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279 | (5) |
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12.2 Finite State Machines |
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284 | (8) |
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12.3 RAMs and Register Banks |
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292 | (5) |
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297 | (4) |
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301 | (26) |
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301 | (1) |
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13.2 Combinational Test Bench |
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302 | (3) |
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305 | (2) |
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307 | (3) |
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13.5 Other Standard Types |
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310 | (2) |
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312 | (2) |
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13.7 Printing Response Values |
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314 | (1) |
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13.8 Using TextIO to Read Data Files |
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315 | (3) |
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13.9 Reading Standard Types |
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318 | (1) |
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13.10 TextIO Error Handling |
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319 | (2) |
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13.11 TextIO for Synthesis Types |
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321 | (1) |
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13.12 TextIO for User-Defined Types |
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322 | (3) |
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325 | (2) |
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327 | (10) |
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327 | (1) |
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328 | (1) |
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329 | (1) |
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330 | (3) |
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14.5 Organising Your Files |
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333 | (2) |
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14.6 Incremental Compilation |
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335 | (2) |
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337 | (32) |
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337 | (1) |
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338 | (2) |
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340 | (12) |
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352 | (1) |
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353 | (8) |
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15.6 Floating-Point Version |
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361 | (1) |
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362 | (2) |
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364 | (2) |
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366 | (3) |
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Appendix A Package Listings |
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369 | (70) |
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369 | (4) |
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A.2 Package Standard_Additions |
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373 | (7) |
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A.3 Package Std_Logic_1164 |
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380 | (3) |
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A.4 Package Std_Logic_1164_Additions |
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383 | (6) |
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389 | (4) |
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A.6 Package Numeric_Std_Additions |
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393 | (7) |
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A.7 Package Fixed_Float_Types |
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400 | (1) |
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401 | (14) |
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415 | (14) |
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429 | (2) |
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A.11 Package Standard_Textio_Additions |
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431 | (1) |
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A.12 Package Std_Logic_Arith |
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432 | (4) |
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436 | (3) |
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Appendix B Syntax Reference |
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439 | (10) |
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439 | (1) |
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440 | (1) |
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B.3 Concurrent Statements |
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441 | (2) |
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B.4 Sequential Statements |
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443 | (1) |
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444 | (1) |
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445 | (4) |
References |
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449 | (2) |
Index |
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451 | |