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E-raamat: VHDL for Logic Synthesis

  • Formaat: PDF+DRM
  • Ilmumisaeg: 08-Mar-2011
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9780470977927
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  • Formaat: PDF+DRM
  • Ilmumisaeg: 08-Mar-2011
  • Kirjastus: John Wiley & Sons Inc
  • Keel: eng
  • ISBN-13: 9780470977927

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Making VHDL a simple and easy-to-use hardware description language

Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types.

This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.

Features to this edition include:





a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies a design style that results in long design lifetimes, maximum design reuse and easy technology retargeting a new chapter on a large scale design example based on a digital filter from design objective and design process, to testing strategy and test benches a chapter on writing test benches, with everything needed to implement a test-based design strategy extensive coverage of data path design, including integer, fixed-point and floating-point arithmetic, logic circuits, shifters, tristate buses, RAMs, ROMs, state machines, and decoders

Focused specifically on logic synthesis, this book is for professional hardware engineers using VHDL for logic synthesis, and digital systems designers new to VHDL but familiar with digital systems. It offers all the knowledge and tools needed to use VHDL for logic synthesis. Organised in themed chapters and with a comprehensive index, this complete reference will also benefit postgraduate students following courses on microelectronics or VLSI / semiconductors and digital design.
Preface xi
List of Figures
xv
List of Tables
xvii
1 Introduction
1(6)
1.1 The VHDL Design Cycle
1(1)
1.2 The Origins of VHDL
2(1)
1.3 The Standardisation Process
3(1)
1.4 Unification of VHDL Standards
4(1)
1.5 Portability
4(3)
2 Register-Transfer Level Design
7(12)
2.1 The RTL Design Stages
8(1)
2.2 Example Circuit
8(2)
2.3 Identify the Data Operations
10(2)
2.4 Determine the Data Precision
12(1)
2.5 Choose Resources to Provide
12(1)
2.6 Allocate Operations to Resources
13(1)
2.7 Design the Controller
14(1)
2.8 Design the Reset Mechanism
15(1)
2.9 VHDL Description of the RTL Design
15(1)
2.10 Synthesis Results
16(3)
3 Combinational Logic
19(18)
3.1 Design Units
19(1)
3.2 Entities and Architectures
20(2)
3.3 Simulation Model
22(3)
3.4 Synthesis Templates
25(2)
3.5 Signals and Ports
27(2)
3.6 Initial Values
29(1)
3.7 Simple Signal Assignments
30(1)
3.8 Conditional Signal Assignments
31(2)
3.9 Selected Signal Assignment
33(1)
3.10 Worked Example
34(3)
4 Basic Types
37(26)
4.1 Synthesisable Types
37(1)
4.2 Standard Types
37(1)
4.3 Standard Operators
38(1)
4.4 Type Bit
39(1)
4.5 Type Boolean
39(2)
4.6 Integer Types
41(5)
4.7 Enumeration Types
46(1)
4.8 Multi-Valued Logic Types
47(1)
4.9 Records
48(1)
4.10 Arrays
49(4)
4.11 Aggregates, Strings and Bit-Strings
53(3)
4.12 Attributes
56(4)
4.13 More on Selected Signal Assignments
60(3)
5 Operators
63(22)
5.1 The Standard Operators
63(1)
5.2 Operator Precedence
64(6)
5.3 Boolean Operators
70(3)
5.4 Comparison Operators
73(3)
5.5 Shifting Operators
76(3)
5.6 Arithmetic Operators
79(5)
5.7 Concatenation Operator
84(1)
6 Synthesis Types
85(66)
6.1 Synthesis Type System
85(2)
6.2 Making the Packages Visible
87(3)
6.3 Logic Types-Std_Logic_1164
90(5)
6.4 Numeric Types - Numeric_Std
95(10)
6.5 Fixed-Point Types - Fixed_Pkg
105(14)
6.6 Floating-Point Types - Float_Pkg
119(15)
6.7 Type Conversions
134(10)
6.8 Constant Values
144(2)
6.9 Mixing Types in Expressions
146(1)
6.10 Top-Level Interface
147(4)
7 Std_Logic_Arith
151(16)
7.1 The Std_Logic_Arith Package
151(1)
7.2 Contents of Std_Logic_Arith
152(9)
7.3 Type Conversions
161(1)
7.4 Constant Values
162(2)
7.5 Mixing Types in Expressions
164(3)
8 Sequential VHDL
167(24)
8.1 Processes
167(3)
8.2 Signal Assignments
170(1)
8.3 Variables
171(1)
8.4 If Statements
172(5)
8.5 Case Statements
177(1)
8.6 Latch Inference
178(3)
8.7 Loops
181(6)
8.8 Worked Example
187(4)
9 Registers
191(22)
9.1 Basic D-Type Register
191(1)
9.2 Simulation Model
192(1)
9.3 Synthesis Model
193(2)
9.4 Register Templates
195(4)
9.5 Register Types
199(1)
9.6 Clock Types
199(1)
9.7 Clock Gating
200(1)
9.8 Data Gating
201(2)
9.9 Asynchronous Reset
203(5)
9.10 Synchronous Reset
208(2)
9.11 Registered Variables
210(1)
9.12 Initial Values
211(2)
10 Hierarchy
213(30)
10.1 The Role of Components
213(1)
10.2 Indirect Binding
214(5)
10.3 Direct Binding
219(1)
10.4 Component Packages
220(2)
10.5 Parameterised Components
222(3)
10.6 Generate Statements
225(5)
10.7 Worked Examples
230(13)
11 Subprograms
243(36)
11.1 The Role of Subprograms
243(1)
11.2 Functions
243(11)
11.3 Operators
254(4)
11.4 Type Conversions
258(3)
11.5 Procedures
261(6)
11.6 Declaring Subprograms
267(3)
11.7 Worked Example
270(9)
12 Special Structures
279(22)
12.1 Tristates
279(5)
12.2 Finite State Machines
284(8)
12.3 RAMs and Register Banks
292(5)
12.4 Decoders and ROMs
297(4)
13 Test Benches
301(26)
13.1 Test Benches
301(1)
13.2 Combinational Test Bench
302(3)
13.3 Verifying Responses
305(2)
13.4 Clocks and Resets
307(3)
13.5 Other Standard Types
310(2)
13.6 Don't Care Outputs
312(2)
13.7 Printing Response Values
314(1)
13.8 Using TextIO to Read Data Files
315(3)
13.9 Reading Standard Types
318(1)
13.10 TextIO Error Handling
319(2)
13.11 TextIO for Synthesis Types
321(1)
13.12 TextIO for User-Defined Types
322(3)
13.13 Worked Example
325(2)
14 Libraries
327(10)
14.1 The Library
327(1)
14.2 Library Names
328(1)
14.3 Library Work
329(1)
14.4 Standard Libraries
330(3)
14.5 Organising Your Files
333(2)
14.6 Incremental Compilation
335(2)
15 Case Study
337(32)
15.1 Specification
337(1)
15.2 System-Level Design
338(2)
15.3 RTL Design
340(12)
15.4 Trial Synthesis
352(1)
15.5 Testing the Design
353(8)
15.6 Floating-Point Version
361(1)
15.7 Final Synthesis
362(2)
15.8 Generic Version
364(2)
15.9 Conclusions
366(3)
Appendix A Package Listings
369(70)
A.1 Package Standard
369(4)
A.2 Package Standard_Additions
373(7)
A.3 Package Std_Logic_1164
380(3)
A.4 Package Std_Logic_1164_Additions
383(6)
A.5 Package Numeric_Std
389(4)
A.6 Package Numeric_Std_Additions
393(7)
A.7 Package Fixed_Float_Types
400(1)
A.8 Package Fixed_Pkg
401(14)
A.9 Package Float_Pkg
415(14)
A.10 Package TextIO
429(2)
A.11 Package Standard_Textio_Additions
431(1)
A.12 Package Std_Logic_Arith
432(4)
A.13 Package Math_Real
436(3)
Appendix B Syntax Reference
439(10)
B.1 Keywords
439(1)
B.2 Design Units
440(1)
B.3 Concurrent Statements
441(2)
B.4 Sequential Statements
443(1)
B.5 Expressions
444(1)
B.6 Declarations
445(4)
References 449(2)
Index 451
Andrew Rushton, TransEDA Ltd., Southampton, UK Dr Rushton previously worked as an industrial hardware engineer at TransEDA Ltd., the leader in Verification Closure Measurement solutions for electronic designs. He now runs his own website design and programming consultancy company, www.andyrushton.co.uk.