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Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM |
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1 | (9) |
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Santosh Kumar Vishvakarma |
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A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator |
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10 | (9) |
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A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier |
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19 | (7) |
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An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network |
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26 | (9) |
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Computational Functions' VLSI Implementation for Compressed Sensing |
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35 | (9) |
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A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization |
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44 | (5) |
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Esakkimuthu Dhakshinamoorthy |
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An Area Efficient Wide Range On-Chip Delay Measurement Architecture |
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49 | (10) |
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10 Gbps Current Mode Logic I/O Buffer |
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59 | (7) |
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Kapees: A New Tool for Standard Cell Placement |
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66 | (8) |
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Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization |
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74 | (9) |
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Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence |
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83 | (11) |
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Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application |
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94 | (6) |
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Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology |
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100 | (8) |
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Characterization of Logical Effort for Improved Delay |
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108 | (10) |
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A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance |
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118 | (10) |
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An Improved gm/ID Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design |
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128 | (10) |
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An Efficient RF Energy Harvester with Tuned Matching Circuit |
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138 | (8) |
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A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual - Tox in CMOS VLSI Circuits |
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146 | (7) |
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Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET |
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153 | (7) |
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Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG) |
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160 | (9) |
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Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs |
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169 | (8) |
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A Combined CMOS Reference Circuit with Supply and Temperature Compensation |
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177 | (8) |
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Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology |
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185 | (9) |
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A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures |
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194 | (10) |
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Random-LRU: A Replacement Policy for Chip Multiprocessors |
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204 | (10) |
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Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations |
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214 | (9) |
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Congestion Balancing Global Router |
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223 | (10) |
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CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions |
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233 | (9) |
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Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption |
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242 | (7) |
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Modeling of High Frequency Out-of-Plane Single Axis MEMS Capacitive Accelerometer |
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249 | (8) |
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CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time |
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257 | (10) |
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Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers |
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267 | (7) |
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On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics |
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274 | (10) |
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Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool |
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284 | (10) |
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A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup |
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294 | (10) |
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Fault Aware Dynamic Adaptive Routing Using LBDR |
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304 | (8) |
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Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with Its Peripherals |
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312 | (10) |
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On Designing Testable Reversible Circuits Using Gate Duplication |
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322 | (8) |
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Circuit Transient Analysis Using State Space Equations |
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330 | (7) |
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3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter |
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337 | (8) |
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Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP |
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345 | (8) |
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Design and Optimization of a 2x2 Directional Micro-strip Patch Antenna |
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353 | (8) |
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A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips |
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361 | (15) |
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Defect Diagnosis of Digital Circuits Using Surrogate Faults |
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376 | (11) |
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| Author Index |
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387 | |
Lisainfo e-raamatute kohta