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E-raamat: Wafer-Level Testing and Test During Burn-In for Integrated Circuits

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  • Formaat: 210 pages
  • Ilmumisaeg: 31-Jan-2010
  • Kirjastus: Artech House Publishers
  • ISBN-13: 9781596939905
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Wafer-Level Testing and Test During Burn-In for Integrated CircuitsSuurem pilt
  • Formaat: 210 pages
  • Ilmumisaeg: 31-Jan-2010
  • Kirjastus: Artech House Publishers
  • ISBN-13: 9781596939905
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This analysis of methods for subjecting integrated circuits and semiconductor devices to electrical testing and stress testing will serve as a tutorial for engineers working with automatic test equipment. It shows how wafer-level testing during burn-in (WLTBI) helps lower product costs and increase quality in semiconductor manufacturing. Two introductory chapters offer background on testing and trends in WLTBI. The rest of the book details five methods, including resource-constrained testing of core-based SoCs, defect screening for mixed-signal SoCs, and power management by test-pattern ordering. The book also addresses the issue of testing next-generation products with previous-generation testers. A list of symbols and acronyms is included. Bahukudumbi is a quality and reliability test engineer at Intel Corporation. Chakrabarty teaches in the Department of Electrical and Computer Engineering at Duke University. Annotation ©2010 Book News, Inc., Portland, OR (booknews.com)
Preface xiii
Acknowledgements xv
Introduction
1(24)
Background
4(5)
System-Level Design-for-Test and Test Scheduling for Core-Based SoCs
4(2)
Wafer-Level Test During Burn-In
6(3)
Scan Design
9(1)
Key Drivers for Wafer-Level Test and Burn-In
9(7)
Challenges Associated with Wafer Sort
10(1)
Emergence of KGDs
11(1)
WLTBI: Industry Adoption and Challenges
11(5)
Wafer-Level Test Planning for Core-Based SoCs
16(1)
Wafer-Level Defect Screening for Mixed-Signal SoCs
17(1)
WLTBI of Core-Based SoCs
17(1)
Power Management for WLTBI
18(1)
How This Book is Organized
18(7)
References
20(5)
Wafer-Level Test and Burn-In: Industry Practices and Trends
25(24)
Overview and Definitions
25(4)
Status of Wafer-Level Test and WLBI
29(2)
Wafer-Level Burn-In
31(2)
Doing Both Wafer-Level Test and Wafer-Level Burn-In
33(12)
Practical Matters
34(1)
Volumes Needed
34(2)
Power per Die and per Wafer
36(1)
Types of Die That Can Be Tested and Burned-In
36(1)
Functional Tests Versus Parametric Tests
36(1)
Number of Contacts per Die
37(1)
Number of Signal Channels Needed
37(1)
Single-Pass Versus Multiple Pass
38(1)
Maximum Force per Wafer
38(1)
Contact Method
39(1)
Contact Life
40(1)
Minimizing Costs for SDBs and Contactors
41(1)
Bumped Wafers Versus Wafers with Bond Pads
41(1)
Pitch
41(1)
Pad Size
42(1)
Coplanarity
43(1)
Background (Thinned) Wafers and Plastic-Backed Wafers
43(1)
More Than One Die Type on the Wafer
43(1)
Changing Cartridges
43(1)
Test Electronics
44(1)
Die Power and Shorted Die
44(1)
Current per Die and per Wafer
44(1)
Voltage Levels Needed
45(1)
Clock and Pattern Frequencies
45(1)
Wafer Maps and Binning
45(1)
Future Projections
45(4)
References
46(3)
Resource-Constrained Testing of Core-Based SoCs
49(42)
Defect Probability Estimation for Embedded Cores
51(5)
Unified Negative-Binomial Model for Yield Estimation
51(1)
Procedure to Determine Core Defect Probabilities
52(4)
Test-Length Selection for Wafer-Level Test
56(9)
Test-Length Selection Problem: pTLS
60(2)
Efficient Heuristic Procedure
62(2)
Greedy Heuristic Procedure
64(1)
Experimental Results
65(7)
Approximation Error in Prs Due to Taylor Series Approximation
68(4)
Test Data Serialization
72(16)
Test-Length and TAM Optimization Problem: PTLTWS
74(2)
Experimental Results: PTLTWS
76(4)
Enumeration-Based TAM Width and Test-Length Selection
80(3)
TAM Width and Test-Length Selection Based on Geometric Programming
83(4)
Approximation Error in Prs
87(1)
Summary
88(3)
References
89(2)
Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs
91(26)
Test Wrapper for Analog Cores
92(2)
Analog Test Wrapper Modes
94(1)
Wafer-Level Defect Screening: Mixed-Signal Cores
94(6)
Signature Analysis: Mean-Signature-Based Correlation (MSBC)
96(1)
Signature Analysis: golden-Signature-Based Correlation (GSBC)
97(3)
Generic Cost Model
100(4)
Correction Factors: Test Escapes and Yield Loss
100(2)
Cost Model: Generic Framework
102(1)
Overall Cost Components
103(1)
Cost Model: Quantitative Analysis
104(9)
Cost Model: Results for ASIC Chip K
105(1)
Cost Model: Results Considering Failures Due to Both Digital and Mixed-Signal Cores
106(2)
Cost Model: Results Considering Failure Distributions
108(5)
Summary
113(1)
Acknowledgments
114(3)
References
114(3)
Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SOCs
117(24)
Cycle-Accurate Power Modeling
119(6)
Transitions in a Scan Chain
120(4)
Transitions in Wrapper Chains
124(1)
Test Scheduling for WLTBI
125(6)
Graph-Matching-Based Approach for Test Scheduling
126(5)
Heuristic Procedure to Solve P Core Order
131(1)
Baseline Methods
132(1)
Experimental Results
132(7)
Summary
139(1)
Acknowldgments
139(2)
References
139(2)
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering
141(22)
Background: Cycle-Accurate Power Modeling
142(2)
Scan-Chain Transition-Count Calculation
142(2)
Test-Pattern Ordering Problem: PTPO
144(4)
Computational Complexity of PTPO
147(1)
Heuristic Methods for Test-Pattern Ordering
148(2)
Baseline Approaches
150(1)
Baseline Method 1: Average Power Consumption
150(1)
Baseline Method 2: Peak Power Consumption
151(1)
Experimental Results
151(4)
Summary
155(8)
References
160(3)
Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation
163(20)
Minimum-Variation X-Fill Problem: PMVF
164(2)
Metrics: Variation in Power Consumption During Test
164(1)
Outline of Proposed Method
165(1)
Framework to Control Power Variation for WLTBI
166(6)
Minimum-Variation X-Filling
166(3)
Eliminating Capture-Power Violations
169(1)
Test-Pattern Ordering for WLTBI
170(1)
Complete Procedure
171(1)
Baseline Approaches
172(3)
Baseline Method 1: Adjacent Fill
172(2)
Baseline Method 2: 0-Fill
174(1)
Baseline Method 3: 1-Fill
174(1)
Baseline Method 4: ATPG-Compacted Test Sets
174(1)
Experimental Results
175(6)
Summary
181(2)
References
182(1)
Conclusions
183(6)
Summary
183(2)
Future Work
185(4)
Integrated Test-Length and Test-Pattern Selection for Core-Based SoCs
185(1)
Multiple Scan-Chain Design for WLTBI
186(1)
Layout-Aware SoC Test Scheduling for WLTBI
186(1)
References
187(2)
List of Symbols 189(2)
List of Acronyms 191(4)
About the Authors 195(2)
Index 197
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