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E-raamat: Bsim4 And Mosfet Modeling For Ic Simulation

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(Synopsys, Usa), (Univ Of California, Berkeley, Usa)
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This book presents the art of advanced MOSFET modeling for integrated circuit simulation and design. It provides the essential mathematical and physical analyses of all the electrical, mechanical and thermal effects in MOS transistors relevant to the operation of integrated circuits. Particular emphasis is placed on how the BSIM model evolved into the first ever industry standard SPICE MOSFET model for circuit simulation and CMOS technology development.The discussion covers the theory and methodology of how a MOSFET model, or semiconductor device models in general, can be implemented to be robust and efficient, turning device physics theory into a production-worthy SPICE simulation model.Special attention is paid to MOSFET characterization and model parameter extraction methodologies, making the book particularly useful for those interested or already engaged in work in the areas of semiconductor devices, compact modeling for SPICE simulation, and integrated circuit design.
Forword vii
Preface xi
Chapter 1 BSIM and IC Simulation
1(12)
1.1 Circuit Simulation and Compact Models
1(1)
1.2 BSIM - The Beginning
1(2)
1.3 BSIM3 - A Compact Model Based on New MOSFET Physics
3(2)
1.4 BSIM3v3 - World's First MOSFET Standard Model
5(1)
1.5 BSIM4 - Aimed for 130nm Down to 20nm Nodes
6(1)
1.6 BSIM SOI
7(1)
1.7 Impact of BSIM
7(1)
1.8 Looking Towards the Future - The Multi-Gate MOSFET Model
8(1)
1.9 The Intent of This Book
References
9(4)
Chapter 2 Fundamental MOSFET Physical Effects and Their Models for BSIM4
13(74)
2.1 Introduction and
Chapter Objectives
13(1)
2.2 Gate and Channel Geometries and Materials
14(7)
2.2.1 Gate and Channel Lengths and Widths
14(2)
2.2.2 Model Card and Parameter Binning
16(2)
2.2.3 Gate Stack and Substrate Material Model Options
18(3)
2.3 Temperature-Dependence Model Options
21(1)
2.4 Threshold Voltage
22(20)
2.4.1 Long Channel with Uniform Substrate Doping
22(3)
2.4.2 Short-Channel Effect: Vth Roll-Off and Drain Bias Effects
25(6)
2.4.3 Narrow-Width Effects
31(1)
2.4.4 Non-Uniform Substrate Doping
32(1)
2.4.4.1 Non-Uniform Vertical Doping
33(3)
2.4.4.2 Non-Uniform Lateral Doping: Pocket Implants
36(3)
2.4.5 Vth Temperature Dependence
39(1)
2.4.6 BSIM4 Vth Equation
40(2)
2.5 Poly-Silicon Gate Depletion
42(3)
2.6 Bulk-Charge Effects
45(1)
2.7 LDD Resistances
46(5)
2.8 Finite Charge Thickness
51(2)
2.9 Effective Mobility
53(5)
2.10 Layout-Dependent Effects: Mechanical Stress and Proximity Effects
58(8)
2.11
Chapter Summary
66(1)
2.12 Parameter Table
66(21)
References
85(2)
Chapter 3 Channel DC Current and Output Resistance
87(28)
3.1 Introduction and
Chapter Objectives
87(1)
3.2 Channel Current Theory
88(1)
3.3 Single Continuous Channel Charge Model
89(4)
3.4 Channel Current in Subthreshold and Linear Operations
93(2)
3.5 Velocity Saturation and Velocity Overshoot
95(3)
3.6 Output Resistance in Saturation Region
98(9)
3.6.1 CLM: Channel Length Modulation
100(3)
3.6.2 DIBL: Drain-Induced Barrier Lowering
103(1)
3.6.3 DITS: Drain-Induced Threshold Voltage Shift Due to Non-Uniform Doping
104(1)
3.6.4 SCBE: Substrate Current Induced Body-Bias Effect
105(1)
3.6.5 Channel Current Model for All Regions of Operation
106(1)
3.7 Source-End Velocity Limit
107(1)
3.8
Chapter Summary
108(1)
3.9 Parameter Table
109(6)
References
113(2)
Chapter 4 Gate Direct-Tunneling and Body Currents
115(40)
4.1 Introduction and
Chapter Objectives
115(1)
4.2 Gate Direct-Tunneling Current Theory and Model
116(22)
4.2.1 Tunneling Mechanisms and Current Components
116(4)
4.2.2 Gate Oxide Voltage
120(1)
4.2.3 Gate-Body Tunneling Current Igb
121(2)
4.2.4 Gate-Source/Drain Tunneling Through Overlap Regions
123(2)
4.2.5 Gate-Channel Tunneling Current
125(1)
4.2.5.1 Igc0: The Vds = 0 Bias Scenario
125(2)
4.2.5.2 Igcs and Igcd Partitioning: The Non-Zero Vds Scenario
127(10)
4.2.6 Characterization and Parameter Extraction
137(1)
4.3 Body Currents
138(9)
4.3.1 Impact Ionization
139(4)
4.3.2 Gate-Induced Source and Drain Leakage
143(4)
4.4 Summary of BSIM4 Branch and Terminal DC Currents
147(1)
4.5
Chapter Summary
148(1)
4.6 Parameter Table
149(6)
References
152(3)
Chapter 5 Charge and Capacitance Models
155(34)
5.1 Introduction and
Chapter Objectives
155(2)
5.2 MOSFET Capacitance Theory
157(10)
5.3 Intrinsic Charge and Capacitance Models
167(13)
5.3.1 Charge-Thickness Model (CTM)
168(8)
5.3.2 CAPMOD = 2 Charge Model Formulations
176(4)
5.4 Fringing and Overlap Capacitances
180(3)
5.4.1 Fringing Capacitances
180(1)
5.4.2 Overlap Capacitances
181(2)
5.5
Chapter Summary
183(1)
5.6 Parameter Table
184(5)
References
186(3)
Chapter 6 Non-Quasi-Static and Parasitic Gate and Body Resistances
189(46)
6.1 Introduction and
Chapter Objectives
189(1)
6.2 Gate Electrode Resistance
190(3)
6.3 Gate Intrinsic-Input Resistance for Non-Quasi-Static Modeling
193(8)
6.4 Charge-Deficit Transient and AC NQS Models
201(13)
6.4.1 Charge-Deficit Transient NQS Model
201(10)
6.4.2 Charge-Deficit AC NQS Model
211(3)
6.5 Body Resistance Network
214(12)
6.5.1 RBODYMOD = 1: A Local Network
216(2)
6.5.2 RBODYMOD = 2: A Scalable Network
218(1)
6.5.2.1 The 5-R Model
219(5)
6.5.2.2 The 3-R Model
224(1)
6.5.2.3 The 1-R Model
225(1)
6.6
Chapter Summary
226(1)
6.7 Parameter Table
227(8)
References
233(2)
Chapter 7 Noise Models
235(34)
7.1 Introduction and
Chapter Objectives
235(1)
7.2 Noise Representations and Parameters
236(10)
7.2.1 Noise and Power Spectral Intensity
236(2)
7.2.2 SPICE Noise Representations
238(1)
7.2.3 Noise Representation and Parameters of a Two-Port Network
239(7)
7.3 BSIM4 Flicker Noise Models
246(7)
7.3.1 The FNOIMOD = 0 Simple Flicker Noise Model
248(1)
7.3.2 The FNOIMOD = 1 Physics-Based, Unified Flicker noise Model
248(5)
7.4 BSIM4 Channel Thermal Noise Models
253(10)
7.4.1 The TNOIMOD = 0 Charge-Based Model
254(1)
7.4.2 The TNOIMOD = 1 Holistic Thermal Noise Model
255(8)
7.5 Other Noise Sources
263(1)
7.6
Chapter Summary
263(1)
7.7 Parameter Table
264(5)
References
266(3)
Chapter 8 Source and Drain Parasitics: Layout-Dependence Model
269(34)
8.1 Introduction and
Chapter Objectives
269(1)
8.2 Connections of a Multi-Transistor Stack
270(3)
8.3 Source and Drain of a Transistor With Multiple Gate Fingers
273(2)
8.4 GEOMOD: The End-Source and End-Drain of a Multi-Finger Transistor
275(1)
8.5 Source and Drain Area and Perimeter Calculation
276(14)
8.6 Saturation Junction Leakage Current and Zero-Bias Capacitance Models
290(2)
8.7 Source and Drain Contact Scenarios and Diffusion Resistances
292(4)
8.8 RGEOMOD: Selecting A Source and Drain Contact Scenario for GEOMOD
296(2)
8.9
Chapter Summary
298(1)
8.10 Parameter Table
298(5)
Chapter 9 Junction Diode IV and CV Models
303(42)
9.1 Introduction and
Chapter Objectives
303(1)
9.2 Physical Mechanisms of Diode DC Currents
303(8)
9.2.1 Shockley-Read-Hall (SRH) Generation and Recombination
305(2)
9.2.2 Trap-Assisted Tunneling (TAT)
307(1)
9.2.3 Band-To-Band Tunneling (BTBT)
308(1)
9.2.4 Diode Breakdown
309(2)
9.3 BSIM4 Diode DC IV Model [ 4]
311(10)
9.3.1 DIOMOD = 0
311(4)
9.3.2 DIOMOD = 1
315(1)
9.3.3 DIOMOD = 2
316(5)
9.4 BSIM4 Junction Leakage Due to Trap-Assisted Tunneling [ 4]
321(1)
9.5 BSIM4 Diode Charge and Capacitance [ 4]
322(6)
9.5.1 BSIM4 Diode CV Model [ 4]
323(5)
9.6 Diode Temperature-Dependence Model [ 4]
328(5)
9.6.1 Temperature-Dependence Model for Diode IV
329(3)
9.6.2 Diode CV Temperature-Dependence Model
332(1)
9.7
Chapter Summary
333(1)
9.8 Parameter Table
333(12)
References
343(2)
Chapter 10 SPICE Implementation Example: The Methodology with BSIM4 Transient NQS
345(42)
10.1 Introduction and
Chapter Objectives
345(1)
10.2 Review of the Charge-Deficit Transient NQS Model
346(1)
10.3 Time Discretization, Equation Linearization and Matrix Stamping
347(26)
10.3.1 Discretization and Linearization of ich_qs(t)
351(5)
10.3.2 Stamping of ich_qs(t)
356(1)
10.3.3 Linearization of iCτnqs (t)
357(1)
10.3.4 Stamping of iCτnqs (t)
357(1)
10.3.5 Linearization of iRτnqs (t)
358(2)
10.3.6 Stamping of iRτnqs (t)
360(1)
10.3.7 Linearization of ig (t)
361(2)
10.3.8 Stamping of ig (t)
363(1)
10.3.9 Linearization of id (t)
363(3)
10.3.10 Stamping of id (t)
366(2)
10.3.11 Linearization of is (t)
368(3)
10.3.12 Stamping of is (t)
371(2)
10.4 Composite Stamps for Transient NQS Model
373(2)
10.5 Bypass
375(7)
10.6 Convergence Checking
382(3)
10.7
Chapter Summary
385(2)
References
386(1)
Chapter 11 Multi-Gate Transistor Model
387(24)
11.1 Introduction and
Chapter Objectives
387(1)
11.2 Advantages of FinFETs Over Planar CMOS
388(2)
11.3 BSIM-CMG
390(16)
11.3.1 The Core Model: Surface Potential Modeling
390(6)
11.3.2 Channel I-V Model
396(3)
11.3.3 Charge and Capacitance Models
399(4)
11.3.4 Modeling of Advanced Physical Effects
403(3)
11.4 Model Validation
406(3)
11.5
Chapter Summary
409(2)
References
409(2)
Index 411
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