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E-raamat: Exploring Memory Hierarchy Design with Emerging Memory Technologies

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Exploring Memory Hierarchy Design with Emerging Memory TechnologiesSuurem pilt
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This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, and FBDRAM.

This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, and FBDRAM.

This book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc. The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the “memory wall.” The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification; hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named “Moguls” is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.
1 Introduction
1(12)
1.1 Motivation
1(2)
1.1.1 Requirements of Large Memory and High Bandwidth
1(1)
1.1.2 Increasing Power Consumption
2(1)
1.1.3 Vulnerability to Soft Errors
3(1)
1.2 Background of Emerging Memory Technologies
3(4)
1.2.1 MRAM Technology
4(2)
1.2.2 PRAM Technology
6(1)
1.3 Challenges and Prior Related Work
7(1)
1.4 Goals of this Book
8(1)
1.5 The Organization of this Book
9(4)
References
9(4)
2 Replacing Different Levels of the Memory Hierarchy with NVMs
13(56)
2.1 Introduction
13(1)
2.2 3D Stacked STTRAM L2 Caches
14(20)
2.2.1 Modeling an STTRAM Based Cache
15(1)
2.2.2 Configurations and Assumptions
16(3)
2.2.3 Replacing SRAM with STTRAM as L2 Caches
19(3)
2.2.4 Novel 3D-Stacked Cache Architecture
22(11)
2.2.5 DRAM Caches Versus MRAM Caches
33(1)
2.3 Frequent-Value Based PCM Memory
34(13)
2.3.1 Concept of Frequent-Value
34(1)
2.3.2 Frequent-Value Based PRAM Memory
35(4)
2.3.3 Profiling and Management of Frequent Values
39(3)
2.3.4 Complementing with Available Techniques
42(1)
2.3.5 Evaluations
43(4)
2.4 Hybrid SSD Using NAND-Flash and PCM
47(17)
2.4.1 Background
48(3)
2.4.2 Overview of the Hybrid Architecture
51(2)
2.4.3 Management Policy of PRAM Log Region
53(3)
2.4.4 Endurance of the Hybrid Architecture
56(2)
2.4.5 Experimental Results
58(6)
2.5
Chapter Summary
64(5)
References
65(4)
3 Moguls: A Model to Explore the Memory Hierarchy for Throughput Computing
69(24)
3.1 Introduction
69(2)
3.2 Moguls Memory Model
71(5)
3.2.1 Problem Description
71(1)
3.2.2 Moguls Memory Model
72(3)
3.2.3 Generation of Provided CB curve
75(1)
3.3 Designing a Memory Hierarchy with Moguls
76(5)
3.3.1 Approximations Used to Apply the Moguls Model
76(1)
3.3.2 Cache Hierarchy Optimized for Energy-Efficiency
77(3)
3.3.3 Throughput with Power Consumption Budget
80(1)
3.3.4 Throughput with Peak Bandwidth Constraint
80(1)
3.4 Memory Hierarchy Design with Hybrid Technologies
81(2)
3.5 Experiments and Validation
83(8)
3.5.1 Experimental Setup
84(2)
3.5.2 Validation of Moguls Model
86(3)
3.5.3 The Analysis of 2-to-2 Approximation
89(1)
3.5.4 Improvements from Hybrid Memory Technologies
90(1)
3.6 Future Work
91(1)
3.7
Chapter Summary
91(2)
References
92(1)
4 Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory
93(26)
4.1 Introduction
93(1)
4.2 Preliminaries
94(3)
4.2.1 ECC Protection
94(1)
4.2.2 Soft Errors of STT-RAM
95(2)
4.3 Architecture Modification
97(8)
4.3.1 Baseline Architecture
97(1)
4.3.2 Replacing L2 and L3 Caches with STT-RAM
98(1)
4.3.3 Replacing L1 Caches with STT-RAM
99(1)
4.3.4 Replacing In-Pipeline Memory Components with STT-RAM
100(3)
4.3.5 Improving Reliability of Logic
103(1)
4.3.6 Tag Array of Caches
104(1)
4.4 Methodology
105(2)
4.4.1 Evaluation Setup
105(1)
4.4.2 Metric for Soft Error Vulnerability
105(2)
4.5 Experimental Results
107(8)
4.5.1 Performance Evaluation
107(2)
4.5.2 Soft Error Vulnerability Analysis
109(2)
4.5.3 Power Consumption
111(2)
4.5.4 Thermal Evaluation
113(2)
4.6
Chapter Summary
115(4)
References
115(4)
5 Conclusions
119(2)
Index 121
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