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E-raamat: Fundamentals of Nanoscaled Field Effect Transistors

  • Formaat: PDF+DRM
  • Sari: Engineering
  • Ilmumisaeg: 23-Apr-2013
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461468226
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Fundamentals of Nanoscaled Field Effect TransistorsSuurem pilt
  • Formaat: PDF+DRM
  • Sari: Engineering
  • Ilmumisaeg: 23-Apr-2013
  • Kirjastus: Springer-Verlag New York Inc.
  • Keel: eng
  • ISBN-13: 9781461468226
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Fundamentals of Nanoscaled Field Effect Transistors gives comprehensive coverage of the fundamental physical principles and theory behind nanoscale transistors. The specific issues that arise for nanoscale MOSFETs, such as quantum mechanical tunneling and inversion layer quantization, are fully explored. The solutions to these issues, such as high-? technology, strained-Si technology, alternate devices structures and graphene technology are also given. Some case studies regarding the above issues and solution are also given in the book.



This book covers principles and theory of nanoscale transistors, including quantum mechanical tunneling and inversion layer quantization and solutions like high-k and strained-Si technology, alternate structures and graphene technology. Includes case studies.
1 Scaling of a MOS Transistor
1(24)
1.1 Introduction
1(1)
1.2 International Technology Road Map for Semiconductor (ITRS) and Its Projections
2(1)
1.3 MOSFET Physics
3(7)
1.3.1 MOSFET Operation
3(2)
1.3.2 Accumulation
5(1)
1.3.3 Depletion
5(1)
1.3.4 Channel Creation (Inversion)
5(1)
1.3.5 Inversion Charge Density
6(1)
1.3.6 Weak Inversion
6(1)
1.3.7 Strong Inversion
7(1)
1.3.8 Explicit Surface Potential
7(1)
1.3.9 Threshold Voltage (VTh)
8(1)
1.3.10 Substrate Bias Effect
8(1)
1.3.11 Drain Current
9(1)
1.4 I-V Characteristics
10(2)
1.4.1 Charge Sheet Model
11(1)
1.5 Gate Capacitance
12(1)
1.6 Scaling of MOSFETs
13(1)
1.6.1 Constant Field Scaling
13(1)
1.6.2 Constant Voltage Scaling
14(1)
1.7 Short Channel Effects or Penalties of Scaling
14(4)
1.7.1 Carrier Field Mobility Reduction
14(1)
1.7.2 Channel Length Modulation (CLM)
15(1)
1.7.3 Drain Induced Barrier Lowering (DIBL)
16(1)
1.7.4 Gate Oxide Tunneling
16(1)
1.7.5 Inversion Layer Quantization
16(1)
1.7.6 Impact Ionization
16(1)
1.7.7 Source and Drain Resistance Effect
17(1)
1.7.8 Poly-Si Depletion Layer Effect
17(1)
1.7.9 Punch-Through Effect
17(1)
1.7.10 Atomistic Effects
18(1)
1.7.11 Thermodynamic Effects
18(1)
1.7.12 Ballistic Effects
18(1)
1.8 MOSFET Models
18(5)
1.8.1 Threshold Voltage Based Model
19(3)
1.8.2 Potential Based Model
22(1)
1.9 Comparison of MOSFET Models
23(1)
1.10 Conclusion
24(1)
2 Nanoscale Effects: Gate Oxide Leakage Currents
25(12)
2.1 Introduction
25(1)
2.2 Gate Oxide Tunneling Phenomenon
26(2)
2.2.1 FN Tunneling in a MOSFET
26(1)
2.2.2 QMDT in a MOSFET
27(1)
2.3 Impact of Gate Oxide Tunneling
28(1)
2.4 Models for QMDT in Gate Oxides
28(2)
2.4.1 BSIM 4 Model
29(1)
2.4.2 Philips MOS Model 11
30(1)
2.4.3 SP Model
30(1)
2.4.4 HiSIM Model
30(1)
2.4.5 EKV Model
30(1)
2.5 Analytical Modeling of QMDT: A Case Study
30(5)
2.5.1 WKB Approximation
31(2)
2.5.2 Gate Oxide Tunneling with Depletion in the Poly-Si Gate
33(2)
2.6 Impact of Other Parameters on QMDT Current Density
35(1)
2.6.1 Tunneling in Germanium (Ge) MOSFETs
35(1)
2.6.2 Impact of Gate Length Effect (Fringing Field Effect) on Gate Oxide QMDT Current Density
35(1)
2.6.3 Impact of Image Force Barrier Lowering on QMDT Current Density
35(1)
2.6.4 Tunneling Impact on the CMOS Circuits
35(1)
2.7 Tunneling in Multiple Gate MOSFETs
36(1)
2.8 Conclusion
36(1)
3 Nanoscale Effects: Inversion Layer Quantization
37(24)
3.1 Introduction
37(1)
3.2 Inversion Layer Quantization in the Substrate
37(3)
3.2.1 Displacement of Inversion Charge Density into the Bulk
38(1)
3.2.2 Poly-Si Gate Depletion and Quantization
39(1)
3.2.3 Threshold Voltage Shift
40(1)
3.3 Inversion Layer Quantization Modeling Approaches
40(1)
3.4 Inversion Layer Quantization Existing Models
41(7)
3.4.1 Numerical Models
41(1)
3.4.2 Empirical Models
41(1)
3.4.3 Analytical Models
42(3)
3.4.4 Variation Approximation for n-Channel MOSFET
45(2)
3.4.5 Inversion Layer Quantization in p-Channel MOSFET
47(1)
3.4.6 TWA Approach for Hole Quantization
47(1)
3.5 Effect of Crystallography
48(2)
3.6 Inversion Layer Centroid
50(1)
3.7 Inversion Layer Quantization on C-V Characteristics
51(5)
3.7.1 p-Channel MOSFET C-V Modeling
54(1)
3.7.2 C-V Analysis in Poly Quantization
54(2)
3.8 Effect on Threshold Voltage
56(2)
3.9 Effect on Drain Current
58(2)
3.9.1 Impact on Carrier Mobility
59(1)
3.9.2 DIBL Modeling
59(1)
3.10 Conclusion
60(1)
4 Dielectrics for Nanoelectronics
61(12)
4.1 Introduction
61(1)
4.2 Properties of High-κ Dielectrics
62(1)
4.3 Dielectric Types
63(5)
4.3.1 Hafnium Oxide (HfO2)
63(1)
4.3.2 Aluminum Oxide (Al2O3)
63(1)
4.3.3 Lanthanum Oxide (La2O3)
64(1)
4.3.4 Zirconium Oxide (ZrO2)
64(1)
4.3.5 Praseodymium Oxide (Pr2O3)
64(1)
4.3.6 Tantalum Pent Oxide (Ta2O5)
64(1)
4.3.7 Titanium Oxide (TiO2)
64(1)
4.3.8 Yttrium Oxide (Y2O3)
64(4)
4.4 Limitations of High-κ Dielectrics
68(1)
4.4.1 Exact Calculation of EOT
68(1)
4.4.2 Mobility Problem
68(1)
4.4.3 Structural Defects
69(1)
4.4.4 Bandgap and Band Offset
69(1)
4.4.5 Threshold Voltage Pinning
69(1)
4.5 Selection Criterion for High-Kκ Dielectric
69(2)
4.5.1 Permittivity (ε)
69(1)
4.5.2 Thermodynamic Stability on Si
70(1)
4.5.3 Interface Quality
70(1)
4.5.4 Gate Compatibility
70(1)
4.5.5 Reliability
70(1)
4.5.6 Atomic Diffusion
71(1)
4.6 Deposition Techniques
71(1)
4.7 Low-κ Dielectrics
71(1)
4.8 Types of Low-κ Dielectrics
72(1)
4.9 Conclusion
72(1)
5 Germanium Technology
73(12)
5.1 Introduction
73(1)
5.2 Delay Calculation
74(1)
5.3 Ge-MOSFET Existing Models
74(7)
5.3.1 QMEs in Ge-MOSFETs: A Case Study
76(5)
5.4 Ge-MOSFET Structures
81(2)
5.4.1 HfO2 Dielectric Ge-MOSFET
81(1)
5.4.2 Ge Oxy Nitride Gate Dielectric Based Ge-MOSFET
82(1)
5.4.3 GeOI MOSFETs
82(1)
5.4.4 WN/Al2O3/AIN Ge-MOSFETs
82(1)
5.5 Conclusion
83(2)
6 Biaxial s-Si Technology
85(48)
6.1 Introduction
85(1)
6.2 History of Biaxial s-Si Technology
86(1)
6.3 Biaxial Stress
87(2)
6.3.1 Physics of Biaxial Strain
87(1)
6.3.2 Strain Effect on Mobility
88(1)
6.4 Biaxial s-Si MOSFET Structures
89(6)
6.4.1 SiGe MOSFET
89(1)
6.4.2 s-Si MOSFET
90(1)
6.4.3 s-SiGe on Insulator Device Structure
91(1)
6.4.4 Germanium-Free SSOI
91(1)
6.4.5 Hetero-structure MOSFET
92(1)
6.4.6 Fabrication of s-SOI Substrates
93(1)
6.4.7 Supercritical s-Si Technology
94(1)
6.4.8 Hybrid Orientation Technology (HOT)
95(1)
6.5 Carrier Mobility Models for Biaxial s-Si MOSFETs
95(10)
6.5.1 Numerical Mobility Models
95(3)
6.5.2 Empirical Mobility Models
98(4)
6.5.3 Analytical Mobility Models
102(3)
6.6 Analytical Mobility Model: A Case Study of n-Channel MOSFET
105(10)
6.6.1 Effective Electrical Field (Es)
106(1)
6.6.2 Depletion Charge Density (Qd)
106(1)
6.6.3 Hetero-interface I: p-Type Substrate and the SiGe Relaxed Layer p-Type
107(1)
6.6.4 Hetero-interface II: SiGe Relaxed Layer p-Type and p-Type s-Si
108(1)
6.6.5 Hetero-interface III: p-Type s-Si/SiO2
108(1)
6.6.6 Inversion Charge Density (Qi)
109(6)
6.7 Analytical Threshold Voltage Model: A Case Study of n-Channel MOSFET
115(5)
6.8 Analytical Hole Mobility Model: A Case Study of p-Channel s-Si MOSFET
120(11)
6.8.1 Effect of Phonon Scattering on Mobility
121(1)
6.8.2 Effect of Surface Roughness Scattering on Mobility
121(1)
6.8.3 Effect of Coulomb Scattering on Mobility
122(3)
6.8.4 Inversion Hole Density
125(6)
6.9 Conclusion
131(2)
7 Uniaxial s-Si Technology
133(20)
7.1 Introduction
133(1)
7.2 Types of Uniaxial Strain
133(2)
7.2.1 Uniaxial Strain Through SiGe S/D
133(1)
7.2.2 Uniaxial Strain Through Si3N4 Capping Layer
134(1)
7.3 Effect of Strain on Band Structure
135(1)
7.4 Problems of Strain Technology
135(1)
7.5 Current Standard MOSFET Models
135(2)
7.5.1 Charge Based MOSFET Model
136(1)
7.5.2 Potential Based MOSFET Model
137(1)
7.5.3 Conductance Based MOSFET Model
137(1)
7.6 Mobility Models Under Uniaxial Strain
137(1)
7.6.1 Experimental Results
137(1)
7.6.2 Numerical Models
137(1)
7.6.3 Analytical Models
138(1)
7.7 Analytical Model: A Case Study of Electron Mobility Under Uniaxial Strain
138(7)
7.7.1 Phonon Scattering Due to Lattice Vibrations
138(1)
7.7.2 Surface Roughness Scattering
139(1)
7.7.3 Coulomb Scattering Due to Impurity Scattering
139(1)
7.7.4 Effective Surface Electrical Field
140(1)
7.7.5 Depletion Charge Density (Qd)
140(1)
7.7.6 Inversion Charge Density
141(4)
7.8 Analytical Model: A Case Study of p-Channel MOSFET Under Uniaxial Strain
145(5)
7.8.1 Inversion Charge Density
147(3)
7.9 Analytical Model: A Case Study of Threshold Voltage and Drain Current of p-Channel MOSFET Under Uniaxial Strain
150(2)
7.10 Conclusion
152(1)
8 Alternate Structures for Nanoelectronic Applications
153(16)
8.1 Introduction
153(1)
8.2 Si on Insulator (SOI)
153(1)
8.3 Partially Depleted Si on Insulator (PD-SOI)
154(1)
8.4 Fully Depleted SOI (FD-SOI)
155(1)
8.5 Multiple Gate FET (MuGFET)
155(3)
8.5.1 DG-MOSFET
156(1)
8.5.2 Tri-gate Transistors
157(1)
8.5.3 Gate-All-Around FETs (GAA-FET)
157(1)
8.6 Ballistic Effect MOS Transistors
158(2)
8.6.1 Existing Ballistic MOSFET Models
158(2)
8.7 Quantum-Effect Devices
160(3)
8.7.1 Solid-State Nanoelectronic Devices
160(1)
8.7.2 Single-Electron Transistors (SET)
160(1)
8.7.3 Models for an SET
161(1)
8.7.4 Resonant-Tunneling Devices (RT Devices)
162(1)
8.7.5 Theory of Operation
162(1)
8.7.6 Models for RTDs
163(1)
8.8 Hybrid Microelectronic-Nanoelectronic Devices
163(1)
8.9 Quantum Dot (QD) Transistor
164(1)
8.9.1 Models for QDTs
164(1)
8.9.2 Models for QCA
165(1)
8.10 Drawbacks of Solid-State Nanoelectronic Devices
165(1)
8.11 Molecular Electronic Devices
166(1)
8.12 Carbon Nanotube Field-Effect Transistor (CNTFETs)
166(1)
8.12.1 Types of CNTs
167(1)
8.12.2 Disadvantages
167(1)
8.13 Conclusion
167(2)
9 Graphene Technology
169(8)
9.1 Introduction
169(1)
9.2 Evolution of Graphene Technology
170(1)
9.3 Technical Challenges of GFETs
171(2)
9.3.1 High-κ Dielectric Growth
171(1)
9.3.2 Fabrication
172(1)
9.3.3 Bandgap
172(1)
9.3.4 Mobility
173(1)
9.3.5 Ohmic Contacts
173(1)
9.4 Graphene FET Models
173(2)
9.5 Strain in GNRFETs
175(1)
9.6 Conclusion
175(2)
Appendix 177(2)
References 179(16)
About the Editor 195(2)
Index 197
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