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E-raamat: MicroCMOS Design

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MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge.

As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and transistor-level design aspects. They must understand abstract concepts associated with large components, such as analog-to-digital converters (ADCs) and phase-locked loops (PLLs). To help readers along, this book discusses topics including:











Amplifier basics & design





Operational amplifier (Opamp)





Data converter basics





Nyquist-rate data converters





Oversampling data converters





High-resolution data converters





PLL basics





Frequency synthesis and clock recovery

Focused more on design than analysis, this reference avoids lengthy equations and instead helps readers acquire a more hands-on mastery of the subject based on the application of core design concepts. Offering the needed perspective on the various design techniques for data converter and PLL design, coverage starts with abstract conceptsincluding discussion of bipolar junction transistors (BJTs) and MOS transistorsand builds up to an examination of the larger systems derived from microCMOS design.
Preface xiii
Acknowledgments xv
The Author xvii
1 Amplifier Basics
1(26)
1.1 Driving-Point and Transfer Functions
1(1)
1.2 Frequency Response
2(3)
1.3 Stability Criteria
5(1)
1.4 Operational Amplifier (Opamp) in Negative Feedback
6(3)
1.5 Phase Margin
9(3)
1.6 Transient Response
12(2)
1.7 Feedback Amplifier
14(2)
1.8 Feedback Effect
16(3)
1.8.1 Linear Range Improvement
18(1)
1.9 Left-Half or Right-Half Plane Zero
19(3)
1.10 Stability of Feedback Amplifiers
22(5)
1.10.1 Frequency-Dependent Feedback Factor
22(5)
2 Amplifier Design
27(34)
2.1 Abstract Low-Frequency Model of Transistors
27(5)
2.1.1 Large Signals
27(1)
2.1.2 Small Signals
28(1)
2.1.3 Transconductance gm and Output Resistance ro
29(1)
2.1.4 Small-Signal Model
30(1)
2.1.5 Body Effect
31(1)
2.2 Driving-Point Resistances at Low Frequencies
32(2)
2.3 Resistance Reflection Rules
34(5)
2.3.1 Local Shunt Feedback
37(2)
2.4 Three Basic Amplifier Configurations
39(2)
2.5 Nine Amplifier Combinations
41(5)
2.5.1 CS-CS
41(1)
2.5.2 CS-CG
41(3)
2.5.3 CS-CD
44(1)
2.5.4 CG-CS, CG-CG, CG-CD
44(1)
2.5.5 CD-CS
45(1)
2.5.6 CD-CG
45(1)
2.5.7 CD-CD
46(1)
2.6 Differential Pair
46(2)
2.6.1 Common-Mode Rejection
46(1)
2.6.2 Symmetric Transfer Function
47(1)
2.7 Gain Boosting
48(3)
2.7.1 Doublet Constraints
49(1)
2.7.2 Other Gain-Boosting Concepts
50(1)
2.8 Biasing
51(3)
2.8.1 Cascode Biasing for Maximum Swing
52(1)
2.8.2 Current Source Matching
53(1)
2.9 Voltage and Current Sources
54(7)
2.9.1 VGS and ΔVGS-Referenced Current Sources
54(1)
2.9.2 Bandgap Reference
55(4)
References
59(2)
3 Operational Amplifier (Opamp)
61(34)
3.1 Small-Signal Model of the Operational Amplifier
61(3)
3.2 Opamp Frequency Compensation
64(5)
3.2.1 Shunt Compensation
64(1)
3.2.2 Pole-Splitting Miller Compensation
65(4)
3.3 Phase Margin of Two-Stage Miller-Compensated Opamps
69(1)
3.4 Right-Half Plane Zero Cancellation in Two-Stage Opamps
70(3)
3.4.1 Inserting a Series Resistance
71(1)
3.4.2 Using Source Follower for Feedback
72(1)
3.4.3 Boosting Gm with Extra Gain Stage
73(1)
3.5 Transient Response of Opamp in Feedback
73(4)
3.5.1 Slew Rate
74(1)
3.5.2 Maximum Power Bandwidth
75(2)
3.6 Opamp Design Examples
77(5)
3.6.1 Telescopic Triple Cascode Opamp
77(2)
3.6.2 Folded-Cascode Opamp
79(1)
3.6.3 Gain-Boosted Cascode Opamp
80(1)
3.6.4 Two-Stage Opamp
81(1)
3.7 Common-Mode Feedback
82(3)
3.7.1 Common-Mode Loop Requirements
83(1)
3.7.2 Continuous-Time Common-Mode Feedback
84(1)
3.8 Offset Cancellation
85(3)
3.9 Opamp Input Capacitance
88(1)
3.10 Opamp Offset
89(2)
3.11 Opamp Noise
91(2)
3.12 Opamp Common-Mode Rejection
93(2)
References
94(1)
4 Data Converter Basics
95(50)
4.1 Analog-to-Digital Converter Basics
95(9)
4.1.1 Aliasing by Sampling
95(1)
4.1.2 Quantization Noise
95(3)
4.1.3 Signal-to-Noise Ratio
98(2)
4.1.4 Differential and Integral Nonlinearity
100(1)
4.1.5 DNL-Related Low-Level Distortion
101(2)
4.1.6 Nyquist-Rate Sampling versus Oversampling
103(1)
4.2 Sample and Hold
104(13)
4.2.1 Charge Injection and Clock Feed-Through
106(1)
4.2.2 Nonlinearity of Sampling Switch
107(1)
4.2.3 Bottom-Plate Sampling
108(2)
4.2.4 Clock Boosting
110(3)
4.2.5 Clock Feed-Through Effect on Offset
113(1)
4.2.6 kT/C Noise and Clock Jitter
114(3)
4.3 Flash Analog-to-Digital Converter
117(3)
4.3.1 Kickback and Sparkle Noise
118(2)
4.4 Comparator
120(6)
4.4.1 Preamplifier
120(3)
4.4.2 Regenerative Latch
123(2)
4.4.3 Comparator Design
125(1)
4.5 ADC Testing
126(3)
4.5.1 ADC Figure of Merit
129(1)
4.6 Averaging and Interpolation Techniques
129(5)
4.6.1 Offset Averaging
129(2)
4.6.2 Interpolation
131(3)
4.7 Low-Voltage Circuit Techniques
134(4)
4.7.1 Low Bound of Analog Supply
134(2)
4.7.2 Switched-Opamp Technique
136(1)
4.7.3 Current-Mode Circuits
136(2)
4.8 Digital-to-Analog Converter Basics
138(7)
4.8.1 DAC Accuracy Considerations
139(1)
4.8.2 Limited Slew Rate
139(2)
4.8.3 Code-Dependent Time Constant
141(1)
4.8.4 Glitches
141(1)
4.8.5 Word Clock Jitter
142(1)
References
142(3)
5 Nyquist-Rate Data Converters
145(54)
5.1 Analog-to-Digital Converter Architectures
145(2)
5.2 Slope-Type ADC
147(2)
5.3 Successive Approximation Register ADC
149(5)
5.3.1 Accuracy Considerations
151(1)
5.3.2 SAR ADC with R + C, C + R, or C + C Combination Digital-to-Analog Converter
151(3)
5.4 Subranging and Multistep ADC
154(3)
5.4.1 Residue
154(2)
5.4.2 Evolution of Multistep and Pipeline Architectures
156(1)
5.5 Pipelined ADC
157(20)
5.5.1 Residue Plot
158(1)
5.5.2 Capacitor-Array Multiplying DAC
159(2)
5.5.3 Accuracy Considerations
161(1)
5.5.4 Digital Correction
162(2)
5.5.5 Generalized N-Bit Pipeline Stage
164(1)
5.5.6 Trilevel Multiplying Digital-to-Analog Converter (MDAC)
165(4)
5.5.7 Capacitor Matching
169(1)
5.5.8 Opamp Gain Requirement
170(2)
5.5.9 Opamp Bandwidth Requirement
172(2)
5.5.10 Noise Considerations
174(1)
5.5.11 Optimum Number of Bits per Stage
174(1)
5.5.12 Scaling Pipelined ADC
175(1)
5.5.13 S/H-Free Pipelined ADC
176(1)
5.6 Folding ADC
177(6)
5.6.1 Accuracy Considerations
179(2)
5.6.2 Cascaded Folding
181(2)
5.7 Other ADCs
183(9)
5.7.1 Algorithmic ADC
183(1)
5.7.2 Time-Interleaving ADC
184(3)
5.7.3 Opamp-Sharing ADC
187(2)
5.7.4 Dynamic Low-Voltage Low-Power Design
189(1)
5.7.5 Time-Domain ADC
190(2)
5.8 Stand-Alone DACs
192(7)
5.8.1 Resistor-String DAC
192(2)
5.8.2 Current-Steering DAC
194(1)
5.8.3 Segmented DAC for Monotonicity
195(1)
References
196(3)
6 Oversampling Data Converters
199(56)
6.1 Concept of Quantizer in Feedback
199(6)
6.1.1 Active Filter by Feedback
199(2)
6.1.2 Loop Stability
201(1)
6.1.3 Quantization Noise Shaping
201(2)
6.1.4 Loop Filter and Bandwidth Requirements
203(2)
6.2 Δ Modulator
205(7)
6.2.1 Quantization Error Estimation
206(1)
6.2.2 Quantization Noise Shaping
207(1)
6.2.3 Signal-to-Quantization Noise
208(1)
6.2.4 Stability and Integrator Overload
209(3)
6.3 High-Order Architectures
212(4)
6.3.1 Direct Multiloop Feedback
212(1)
6.3.2 Single-Loop Feedback
213(2)
6.3.3 Cascaded Modulators
215(1)
6.4 Discrete-Time (DT) versus Continuous-Time (CT) Modulators
216(1)
6.5 Discrete-Time Modulator Design
217(10)
6.5.1 Switched-Capacitor Integrators
217(3)
6.5.2 Multibit Integrator versus Multiplying Digital-to-Analog Converter
220(1)
6.5.3 Multilevel Feedback Digital-to-Analog Converters
221(2)
6.5.4 Design Considerations
223(1)
6.5.5 Broadband Modulators
224(3)
6.6 Band-Pass Modulator Design
227(3)
6.7 Continuous-Time Modulator Design
230(19)
6.7.1 Continuous-Time Δ Modulator
230(1)
6.7.2 Built-in Anti-Aliasing and Blocker Filtering
230(2)
6.7.3 DAC Pulse Position and Pulse Width Jitters
232(2)
6.7.4 Current DAC versus Switched-Capacitor DAC
234(2)
6.7.5 Integrators for SC-DAC
236(1)
6.7.6 Quantizer Meta-Stability
237(1)
6.7.7 CT Modulator Architectures
238(2)
6.7.8 Integrator Design Considerations
240(1)
6.7.9 Gm-C Integrators
241(1)
6.7.10 RC Integrators
241(3)
6.7.11 Feedback Path Design
244(1)
6.7.12 Filter Time-Constant Calibration
245(4)
6.8 Interpolative Oversampling DAC
249(6)
6.8.1 Δ Modulator as Digital Truncator
249(1)
6.8.2 One-Bit or Multibit DAC
250(1)
6.8.3 Monotonic Oversampling Bitstream DAC
251(1)
6.8.4 Postfiltering Requirement
251(1)
References
252(3)
7 High-Resolution Data Converters
255(56)
7.1 Nonlinearity of the Analog-to-Digital Converter
255(4)
7.1.1 Inaccurate Residue in Pipelined Analog-to-Digital Converters
256(1)
7.1.2 Missing Codes and Nonmonotonicity
257(2)
7.2 Evolution of High-Resolution ADC Design
259(4)
7.2.1 Device and Supply Voltage Scaling
259(1)
7.2.2 Broadband High Spurious-Free Dynamic Range Applications
259(1)
7.2.3 High-Resolution ADC Techniques
260(1)
7.2.4 Inherently Linear Analog Techniques
261(1)
7.2.5 Self-Calibration of Successive Approximation Register ADC
262(1)
7.3 Digital Calibration of ADC
263(5)
7.3.1 Digital Calibration Concept
264(1)
7.3.2 Multiplying Digital-to-Analog Converter Capacitor Error Calibration
264(2)
7.3.3 Linear MDAC Gain Error Calibration
266(1)
7.3.4 MDAC Gain Nonlinearity Calibration
267(1)
7.4 Digital Background Calibration
268(10)
7.4.1 Background Capacitor Error Measurement
270(1)
7.4.2 Gain Error Measurement by Pseudo-Random Dithering
271(3)
7.4.3 Constraints in PN Dithering
274(1)
7.4.4 Signal-Dependent PN Dithering
274(4)
7.5 Digital Processing for Gain Nonlinearity
278(6)
7.5.1 Weakly Nonlinear Gain Error
278(1)
7.5.2 Gain Nonlinearity Measurement by PN Dithering
279(1)
7.5.3 Measurement by Signal Correlation
280(1)
7.5.4 Multilevel PN Dithering
281(1)
7.5.5 Accuracy Considerations for Background Error Measurement
281(3)
7.6 Calibration by Zero-Forcing Least-Mean-Square Feedback
284(4)
7.6.1 LMS Feedback Concept
284(1)
7.6.2 Self-Trimming
284(2)
7.6.3 LMS Adaptation for Digital Background Calibration
286(2)
7.7 Calibration of Time-Interleaving ADC
288(3)
7.7.1 Offset Mismatch
288(1)
7.7.2 Gain Mismatch
289(1)
7.7.3 Sample-Time Error
289(2)
7.8 Calibrated Continuous-Time (CT) Δ Modulators
291(14)
7.8.1 Pipeline versus Continuous-Time Δ Modulator
291(1)
7.8.2 Noise Leakage in CT Cascaded Δ Modulator
292(1)
7.8.3 Continuous-Time to Discrete-Time Transform
293(1)
7.8.4 CT-to-DT Transform of Integrators
294(1)
7.8.5 CT-to-DT Transform of Resonators
295(2)
7.8.6 Half-Cycle Delay Effect
297(1)
7.8.7 Noise Transfer Function (NTF) for Single-Loop CT Δ Modulator
298(2)
7.8.8 NCF for CT Cascaded Δ Modulator
300(1)
7.8.9 STF and Built-In Anti-Aliasing in Cascaded CT-DSM
301(1)
7.8.10 Noise Leakage Cancellation in CT Cascaded Modulators
302(1)
7.8.11 Operational Amplifier Finite DC Gain and Bandwidth Effect
303(2)
7.9 Calibration of Current-Steering DAC
305(6)
7.9.1 Static DAC Nonlinearity Error
305(1)
7.9.2 Dynamic DAC Nonlinearity Error
306(1)
7.9.3 DAC in Feedback
307(1)
References
308(3)
8 Phase-Locked Loop Basics
311(56)
8.1 Phase Noise
311(7)
8.1.1 Jitter versus Integrated Root-Mean-Square Phase Noise
312(1)
8.1.2 Amplitude-Modulation to Phase-Modulation Conversion
313(1)
8.1.3 Voltage-Controlled Oscillator Phase Noise
313(2)
8.1.4 Single-Sideband (SSB) and Double-Sideband (DSB) Phase Noises
315(2)
8.1.5 Effect of Frequency Division on Phase Noise
317(1)
8.2 Phase-Locked Loop Operation
318(7)
8.2.1 Linear Model of PLL
319(1)
8.2.2 Second-Order PLL
320(3)
8.2.3 Stability of Second-Order PLL
323(1)
8.2.4 Loop Filter with a Pole and a Zero
324(1)
8.3 Phase Noise Transfer Function
325(6)
8.3.1 SSB Phase Noise Effect on Blocker
327(1)
8.3.2 Integrated Root-Mean-Square Phase Noise Effect on Phase Modulation and Frequency Modulation
328(2)
8.3.3 PLL as FM Demodulator
330(1)
8.4 Phase Detector
331(4)
8.4.1 Multiplier as Phase Detector
331(2)
8.4.2 Up/Down State Machine as Phase Detector
333(1)
8.4.3 Phase Frequency Detector
334(1)
8.5 Charge-Pumped Phase-Locked Loop
335(6)
8.5.1 Stability of Charge-Pumped PLL
336(1)
8.5.2 Loop Filter of Charge-Pumped PLL
336(2)
8.5.3 Reference Spur
338(2)
8.5.4 Charge-Pump Circuits
340(1)
8.6 PLL Bandwidth Constraints
341(4)
8.6.1 Capture and Lock-In Ranges
342(1)
8.6.2 Settling Requirement
343(1)
8.6.3 PLL versus Second-Order Δ Modulator
344(1)
8.7 High-Q LC VCO
345(12)
8.7.1 LC Components in CMOS
345(2)
8.7.2 Oscillation Condition for LC VCO
347(2)
8.7.3 Phase Noise of LC VCO
349(3)
8.7.4 1/f Noise Up-Conversion
352(1)
8.7.5 Low Phase Noise Design for LC VCO
353(1)
8.7.6 Current versus Voltage Limiting
354(2)
8.7.7 Other Noise Sources in PLL
356(1)
8.8 Low-Q Ring-Oscillator VCO
357(7)
8.8.1 Oscillation Condition for Ring-Oscillator VCO
357(1)
8.8.2 Phase Noise of Ring-Oscillator VCO
358(2)
8.8.3 Q Effect on VCO Phase Noise
360(1)
8.8.4 Low Phase Noise Design for Ring-Oscillator VCO
361(3)
8.9 Prescaler
364(3)
8.9.1 Pulse Swallower
365(1)
References
366(1)
9 Frequency Synthesis and Clock Recovery
367(38)
9.1 Phase-Locked Loop Applications
367(2)
9.1.1 General Clock Generation
368(1)
9.1.2 Low-Jitter Clock Generation
368(1)
9.2 Digital PLL
369(2)
9.2.1 Time-to-Digital Converter
370(1)
9.3 Frequency Synthesis
371(9)
9.3.1 Integer-N versus Fractional-N Synthesizers
372(1)
9.3.2 Fractional Spur
373(2)
9.3.3 Spur Cancellation by Digital-to-Analog Converter
375(1)
9.3.4 Spur Shaping by Δ Divider-Ratio Modulator
375(3)
9.3.5 Phase-Frequency Detector/Charge-Pump Nonlinearity
378(1)
9.3.6 Bandwidth Constraint of Fractional-N Synthesizers
379(1)
9.4 Spur-Canceled Fractional-AT Frequency Synthesizer
380(9)
9.4.1 DAC-Based Spur Cancellation
380(3)
9.4.2 Adaptive DAC Gain Calibration
383(1)
9.4.3 Minimum DAC Pulse Width
384(1)
9.4.4 Quantization Noise of the Spur-Canceling DAC
385(1)
9.4.5 Sign-Sign LMS Algorithm
386(1)
9.4.6 Δ Divider Ratio Modulator
386(2)
9.4.7 Calibration of VCO Frequency
388(1)
9.5 Data Symbols
389(4)
9.5.1 Impulse Symbol
390(1)
9.5.2 Binary Pulse Symbol
391(2)
9.6 Data Channel Equalization
393(4)
9.6.1 Linear Equalizer
393(1)
9.6.2 Decision-Feedback Equalizer
394(1)
9.6.3 Zero versus Cosine Equalizers
395(2)
9.7 Clock and Data Recovery
397(4)
9.7.1 CDR with Band-Pass Filter
398(1)
9.7.2 Oversampling Digital CDR
399(1)
9.7.3 Delay-Locked Loop for CDR
399(1)
9.7.4 PLL for CDR
400(1)
9.8 NRZ Phase De tector
401(4)
References
403(2)
Index 405
Bang-Sup Song, Ph.D., received a B.S. from Seoul National University, Korea, in 1973, an M.S. from Korea Advanced Institute of Science in 1975, and a Ph.D. from the University of CaliforniaBerkeley in 1983. From 1975 to 1978, he was a member of the research staff at the Agency for Defense Development, Korea. From 1983 to 1986, he was a member of the technical staff at AT&T Bell Laboratories, Murray Hill, New Jersey, and was also a visiting faculty member in the Department of Electrical Engineering, Rutgers University, New Jersey. From 1986 to 1999, Dr. Song was a professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana. In 1999, Dr. Song joined the faculty of the Department of Electrical and Computer Engineering, University of California, San Diego, where he is endowed with the position of Charles Lee Powell Chair Professor in Wireless Communication.

Dr. Song received a Distinguished Technical Staff Award from AT&T Bell Laboratories in 1986, a Career Development Professor Award from Analog Devices in 1987, and a Xerox Senior Faculty Research Award from the University of Illinois in 1995. His Institute of Electrical and Electronics Engineers (IEEE) activities have been in the capacities of an associate editor and a program committee member for the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems, International Solid-State Circuits Conference, and International Symposium on Circuits and Systems. Dr. Song is an IEEE fellow.
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