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E-raamat: Nano-Semiconductors: Devices and Technology

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Nano-Semiconductors: Devices and TechnologySuurem pilt
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With contributions from top international experts from both industry and academia, Nano-Semiconductors: Devices and Technology is a must-read for anyone with a serious interest in future nanofabrication technologies.

Taking into account the semiconductor industrys transition from standard CMOS silicon to novel device structuresincluding carbon nanotubes (CNT), graphene, quantum dots, and III-V materialsthis book addresses the state of the art in nano devices for electronics. It provides an all-encompassing, one-stop resource on the materials and device structures involved in the evolution from micro- to nanoelectronics.

The book is divided into three parts that address:











Semiconductor materials (i.e., carbon nanotubes, memristors, and spin organic devices) Silicon devices and technology (i.e., BiCMOS, SOI, various 3D integration and RAM technologies, and solar cells) Compound semiconductor devices and technology

This reference explores the groundbreaking opportunities in emerging materials that will take system performance beyond the capabilities of traditional CMOS-based microelectronics. Contributors cover topics ranging from electrical propagation on CNT to GaN HEMTs technology and applications. Approaching the trillion-dollar nanotech industry from the perspective of real market needs and the repercussions of technological barriers, this resource provides vital information about elemental device architecture alternatives that will lead to massive strides in future development.
Preface ix
Editor xi
Contributors xiii
PART I Semiconductor Materials
Chapter 1 Electrical Propagation on Carbon Nanotubes: From Electrodynamics to Circuit Models
3(26)
Antonio Maffucci
Andrea G. Chiariello
Carlo Forestiere
Giovanni Miano
1.1 Introduction
3(2)
1.2 Electrodynamics of CNTs
5(9)
1.2.1 Generality
5(2)
1.2.2 Band Structure of a CNT Shell
7(1)
1.2.3 Constitutive Relation for a CNT Shell
8(3)
1.2.4 Number of Effective Channels for SWCNTs and MWCNTs
11(3)
1.3 An Electromagnetic Application: CNTs as Innovative Scattering Materials
14(4)
1.3.1 Generality
14(1)
1.3.2 Electromagnetic Models for CNT Scattering
14(4)
1.4 Circuital Application: CNTs as Innovative Interconnects
18(8)
1.4.1 CNTs in Nanointerconnects
18(1)
1.4.2 TL Model for a CNT Interconnect
19(3)
1.4.3 A Bundle of CNTs as Innovative Chip-to-Package Interconnects
22(4)
1.5 Conclusions
26(1)
References
27(2)
Chapter 2 Monolithic Integration of Carbon Nanotubes and CMOS
29(38)
Huikai Xie
2.1 Introduction
29(7)
2.1.1 CNT Synthesis
30(1)
2.1.2 CMOS-CNT Integration Challenges and Discussion
31(5)
2.2 CNT Synthesis by Localized Resistive Heating on Mock-CMOS
36(11)
2.2.1 Microheater Design
36(1)
2.2.2 Device Fabrication and Microheater Characterization
37(1)
2.2.2.1 Device Fabrication
37(2)
2.2.2.2 Microheater Characterization
39(5)
2.2.3 Room Temperature CNT Synthesis
44(3)
2.3 Maskless Post-CMOS CNT Synthesis on Foundry CMOS
47(14)
2.3.1 Integration Principles and Device Design
47(5)
2.3.2 Device Fabrication and Characterization
52(5)
2.3.3 On-Chip Synthesis of CNTs
57(1)
2.3.4 Characterization of CNTs and Circuit Evaluations
58(3)
2.4 Conclusion
61(1)
References
61(6)
Chapter 3 Facile, Scalable, and Ambient--Electrochemical Route for Titania Memristor Fabrication
67(20)
Sumit Chaudhary
Nathan M. Neihart
3.1 Introduction
67(2)
3.2 Theory and Device Operation
69(5)
3.3 Applications of Memristors
74(2)
3.4 Current Memristive Materials and Fabrication Technologies
76(3)
3.5 Memristor Fabrication via Electrochemical Anodization
79(2)
3.6 Test Results of Electrochemical Anodization-Based Memristors
81(3)
3.7 Conclusions
84(1)
References
85(2)
Chapter 4 Spin Transport in Organic Semiconductors: A Brief Overview of the First Eight Years
87(50)
Kazi M. Alam
Sandipan Pramanik
4.1 Introduction
88(5)
4.1.1 Spintronics in Data Storage
89(1)
4.1.1.1 GMR Read Heads
89(1)
4.1.1.2 Magnetic Random Access Memory
89(2)
4.1.2 Spintronics for Information Processing
91(1)
4.1.3 Organic Semiconductor Spintronics
92(1)
4.2 Basic Elements of Spin Transport and Implications for Organics
93(12)
4.2.1 Spin Injection
93(3)
4.2.2 Spin Relaxation
96(1)
4.2.2.1 Elliott-Yafet Mechanism
97(1)
4.2.2.2 D'yakonov-Perel' Mechanism
98(1)
4.2.2.3 Bir-Aronov-Pikus Mechanism
98(1)
4.2.2.4 Hyperfine Interaction
99(1)
4.2.3 Spin Relaxation in Organics: General Considerations
100(1)
4.2.4 Measurement of Spin Relaxation Length and Time: Spin Valve Devices
101(4)
4.3 Spin Injection and Transport in Organics: Spin Valve Experiments
105(13)
4.3.1 Organic Thin Films
105(1)
4.3.1.1 Sexithienyl (T6) Thin Films
105(2)
4.3.1.2 Tris 8-Hydroxyquinoline Aluminum (Alq3) Thin Films
107(6)
4.3.1.3 Other Organics
113(1)
4.3.2 Organic Nanowires
114(4)
4.4 Spin Injection and Transport in Organics: Meservey-Tedrow Spin Polarized Tunneling, Two-Photon Photoemission (TPPE), and μSR Experiments
118(4)
4.4.1 Meservey-Tedrow Spin Polarized Tunneling
118(1)
4.4.2 TPPE Spectroscopy
119(1)
4.4.2.1 Background
119(1)
4.4.2.2 Spin Injection and Transport Studies by TPPE Spectroscopy
119(1)
4.4.3 Low-Energy Muon Spin Rotation
120(1)
4.4.3.1 Background
120(1)
4.4.3.2 Measurement of Spin Diffusion Length in Organics by μSR Spectroscopy
121(1)
4.5 Outlook and Conclusion
122(3)
4.5.1 Nonvolatile Memory and Magnetic Field Sensors
123(1)
4.5.2 Spin Based Classical and Quantum Computing
123(1)
4.5.3 Spin Based OLEDs
124(1)
Acknowledgment
125(1)
References
125(12)
PART II Silicon Devices and Technology
Chapter 5 SiGe BiCMOS Technology and Devices
137(16)
Marco Racanelli
Edward Preisler
5.1 Introduction
137(1)
5.2 SiGe HBT Device Physics
138(2)
5.3 Applications Driving SiGe Development
140(1)
5.4 SiGe Performance Metrics
141(3)
5.5 Device Optimization and Roadmap
144(3)
5.6 Modern SiGe BiCMOS RF Platform Components
147(3)
5.7 Conclusions
150(1)
Acknowledgments
150(1)
References
151(2)
Chapter 6 Ultimate FDSOI Multigate MOSFETs and Multibarrier Boosted Gate Resonant Tunneling FETs for a New High-Performance Low-Power Paradigm
153(20)
Aryan Afzalian
6.1 Simulation Algorithm
155(2)
6.2 Gate Coupling Optimization in Nanoscale Nanowire MOSFETs: Electrostatic Versus Quantum Confinement
157(4)
6.3 Physics of RT-FET
161(5)
6.3.1 Influence of Barrier Width
165(1)
6.4 Schottky Barrier RT-FET
166(3)
6.5 Conclusions
169(1)
Acknowledgments
170(1)
References
170(3)
Chapter 7 Development of 3D Chip Integration Technology
173(50)
Katsuyuki Sakuma
7.1 Introduction
174(2)
7.2 3D Integration Technology
176(6)
7.2.1 Advantages of 3D Chip Integration
176(1)
7.2.2 Limitations of 3D Chip Integration
177(1)
7.2.2.1 Thermal Management
177(1)
7.2.2.2 Design Complexity
178(1)
7.2.3 Various Kinds of 3D Technology
178(1)
7.2.4 Approaches for 3D Integration
178(1)
7.2.4.1 Bottom-Up Approach
178(2)
7.2.4.2 Top-Down Approach
180(1)
7.2.5 Key Enabling Technologies for 3D Chip Integration
180(2)
7.3 Through-Silicon Via
182(5)
7.3.1 Processing Flow for TSV
182(1)
7.3.2 Via Etching
182(2)
7.3.3 Insulation Layer
184(1)
7.3.4 Barrier and Adhesion Layer
185(1)
7.3.5 Conductive Materials for TSV
185(2)
7.4 Bonding Technologies
187(16)
7.4.1 Overview of Bonding Technologies
189(2)
7.4.2 IMC Bonding
191(1)
7.4.2.1 Intermetallic System
192(1)
7.4.2.2 Solder Materials for IMC Bonding
193(1)
7.4.3 Characteristics of IMC Bonding
193(1)
7.4.3.1 Test Vehicle for Mechanical Evaluation of IMC Bonding
193(1)
7.4.3.2 Shear Strength
193(2)
7.4.3.3 Shock Test Reliability
195(1)
7.4.3.4 Cross-Section SEM and EDX Analysis
196(2)
7.4.3.5 Thermal Cycle Testing with IMC Bonding
198(2)
7.4.4 Fluxless Bonding
200(1)
7.4.4.1 Ar Plasma Treatment
200(1)
7.4.4.2 Vacuum UV Treatment
200(1)
7.4.4.3 Formic Acid Treatment
201(1)
7.4.4.4 Hydrogen Radical Treatment
201(1)
7.4.4.5 Comparison of Surface Treatments
202(1)
7.5 Die-to-Wafer Integration Technology
203(8)
7.5.1 Die Yield of Stacking Processes
204(1)
7.5.2 Die Cavity Technology
205(2)
7.5.3 Alignment Accuracy
207(1)
7.5.4 Test Vehicle: Design and Features
208(1)
7.5.5 Results of Stacking Using Die Cavity Technology
209(1)
7.5.6 Electrical Tests
210(1)
7.6 Underfill Encapsulation for 3D Integration
211(3)
7.6.1 Overview of Underfill Process
211(1)
7.6.2 Vacuum Underfill Process
212(1)
7.6.3 Results of Vacuum Underfill for 3D Chip Stack
213(1)
7.7 Summary
214(1)
Acknowledgments
215(1)
References
215(8)
Chapter 8 Embedded Spin-Transfer-Torque MRAM
223(24)
Kangho Lee
8.1 Introduction
223(2)
8.1.1 Motivation for Embedded STT-MRAM: Application Perspectives
223(1)
8.1.2 Recent Industrial Efforts for MRAM Development
224(1)
8.2 Magnetic Tunnel Junction: Storage Element of STT-MRAM
225(10)
8.2.1 Magnetization Dynamics in Ferromagnetic Metals
226(3)
8.2.2 Tunneling Magnetoresistance Ratio
229(1)
8.2.3 Energy Barrier for Data Retention
230(1)
8.2.4 Spin-Transfer-Torque (STT Switching)
231(4)
8.3 1T-1MTJ STT-MRAM BITCELL
235(4)
8.3.1 Read Margin
235(2)
8.3.2 Write Margin
237(2)
8.4 MTJ Material Engineering for Write Power Reduction
239(4)
8.4.1 Perpendicular Magnetic Anisotropy
239(3)
8.4.2 Damping Constant and STT Efficiency
242(1)
References
243(4)
Chapter 9 Nonvolatile Memory Device: Resistive Random Access Memory
247(30)
Peng Zhou
Lin Chen
Hangbing Lv
Haijun Wan
Qingqing Sun
9.1 Introduction
248(3)
9.1.1 Resistive Random Access Memory: History and Emerging Technology
248(2)
9.1.2 Challenge for RRAM on Storage-Class Memory
250(1)
9.1.2.1 Performance Requirement
250(1)
9.1.3 Architecture Requirement
251(1)
9.2 BTMO-Based RRAM
251(16)
9.2.1 Device Fabrication and Current-Voltage Characterization
251(1)
9.2.1.1 Device Fabrication
251(2)
9.2.1.2 Current-Voltage Characterization
253(2)
9.2.2 BTMO RRAM Integration for Embedded Application on 0.18 μm Al Process and 0.13 μm Cu Process
255(1)
9.2.2.1 RRAM Integration on 0.18 μm Al Process
255(1)
9.2.2.2 RRAM Integration on 0.13 μm Cu Process
256(3)
9.2.3 Doping Effect in BTMO RRAM
259(2)
9.2.4 Role of Compliance Current
261(4)
9.2.5 Physical Mechanism and Its Evidence
265(2)
9.3 Memristor
267(6)
9.3.1 Leon Chua's Theory of Fourth Fundamental Element
267(3)
9.3.2 HP Laboratories' Discovery of Prototype Pt/TiO2-x/TiO2/Pt Memristor
270(3)
9.4 Conclusion
273(1)
References
273(4)
Chapter 10 DRAM Technology
277(34)
Myoung Jin Lee
10.1 Introduction to Dynamic Random Access Memory
277(5)
10.1.1 DRAM Cell
278(1)
10.1.2 Sense Operation
279(3)
10.2 Sensing Margin in DRAM
282(24)
10.2.1 Definition of Sensing Margin
282(1)
10.2.2 Noise Effect on Sensing Margin
283(1)
10.2.2.1 DRAM Cell Performance (Leakage and Current Drivability)
283(1)
10.2.2.2 High-Performance DRAM Cell Structures
284(9)
10.2.2.3 VTH Mismatch in BLSA
293(1)
10.2.2.4 Sensing Noise in Accordance with Data Pattern
293(2)
10.2.3 Relation between Refresh Time and Sensing Noise in Accordance with Data Pattern
295(5)
10.2.4 How to Improve Sensing Margin
300(1)
10.2.4.1 Offset Compensation Sense Amplifier
301(5)
References
306(5)
Chapter 11 Monocrystalline Silicon Solar Cell Optimization and Modeling
311(24)
Joanne Huang
Victor Moroz
11.1 Introduction
311(1)
11.2 Modeling Optical Effects
312(10)
11.2.1 Textured Surface
312(1)
11.2.2 Behavior of Different Light Wavelengths
313(3)
11.2.3 Optical Performance of Regular Surface Patterns
316(2)
11.2.4 Regular versus Random Texture
318(4)
11.3 Modeling Electronic Effects
322(11)
11.3.1 Definition of Simulation Cell Structure
322(1)
11.3.1.1 Structure Definition
322(1)
11.3.1.2 Meshing Strategy
323(1)
11.3.2 Modeling Methodology
324(1)
11.3.2.1 Impact of Optical Reflectivity on Optically Generated Carrier Profile
324(1)
11.3.2.2 Surface Recombination Rate
324(1)
11.3.2.3 Contact Resistance
324(1)
11.3.2.4 Bulk Recombination
324(2)
11.3.3 Current Crowding
326(1)
11.3.4 Optimizing Efficiency of Solar Cell
327(2)
11.3.5 Comparing 3D with 2D and 1D
329(2)
11.3.6 Junction Optimization
331(2)
11.4 Conclusions
333(1)
References
333(2)
Chapter 12 Radiation Effects on Silicon Devices
335(26)
Marta Bagatin
Simone Gerardin
Alessandro Paccagnella
12.1 Introduction
335(1)
12.2 Radiation Environments
336(3)
12.2.1 Space
336(2)
12.2.2 Terrestrial Environment
338(1)
12.2.3 Man-Made Radiation
339(1)
12.3 TID EFFECTS
339(8)
12.3.1 MOSFETs
342(3)
12.3.2 Bipolar Devices
345(2)
12.4 Displacement Damage
347(3)
12.4.1 Charge-Coupled Devices
349(1)
12.5 Single Event Effects
350(6)
12.5.1 Single Event Upsets in SRAMs
351(3)
12.5.2 SEEs in Flash Cells
354(2)
12.6 Conclusions
356(1)
References
356(5)
PART III Compound Semiconductor Devices and Technology
Chapter 13 GaN/InGaN Double Heterojunction Bipolar Transistors Using Direct-Growth Technology
361(16)
Shyh-Chiang Shen
Jae-Hyun Ryou
Russell Dean Dupuis
13.1 Introduction
361(2)
13.2 GaN/InGaN HBT Design
363(2)
13.3 GaN/InGaN HBT Epitaxial Growth and Fabrication Techniques
365(1)
13.4 State-of-the-Art Direct-Growth GaN/InGaN DHBTs
365(8)
13.4.1 Impact of Indium in InGaN Base Layer
365(4)
13.4.2 Burn-In Effect
369(2)
13.4.3 High-Performance GaN/InGaN DHBT
371(2)
13.5 Technology Development Trends for III-N HBTs
373(1)
References
374(3)
Chapter 14 GaN HEMTs Technology and Applications
377(38)
Geok Ing Ng
Subramaniam Arulkumaran
14.1 Introduction
378(3)
14.2 Device Types and Structures
381(7)
14.2.1 Conventional GaN HEMTs with Cap Layer
381(2)
14.2.2 Advanced GaN HEMTs
383(1)
14.2.2.1 HEMTs with A1N Spacer Layer
383(1)
14.2.2.2 Double Heterostructure HEMTs
383(1)
14.2.2.3 Lattice Matched InA1N/GaN HEMTs
384(1)
14.2.2.4 Quaternary Barrier HEMTs
385(1)
14.2.2.5 N-Face GaN/AlGaN HEMTs
385(2)
14.2.2.6 Field Plate Assisted GaN HEMTs
387(1)
14.2.2.7 GaN Metal-Insulators-Semiconductor HEMTs
388(1)
14.3 Device Fabrication
388(6)
14.3.1 Mesa Isolation
388(2)
14.3.2 Ohmic-Contact Formation
390(2)
14.3.3 Gate Formation by EBL
392(1)
14.3.4 Device Passivation
393(1)
14.3.5 Substrate Thinning and Via-Hole Formation
393(1)
14.4 Device Performance
394(8)
14.4.1 Effects of Passivation
395(1)
14.4.1.1 DC and Pulse I-V Characteristics
395(3)
14.4.1.2 RF Characteristics
398(1)
14.4.2 Temperature-Dependent Characteristics
399(1)
14.4.2.1 DC Characteristics
399(1)
14.4.2.2 RF Characteristics
400(2)
14.5 GaN HEMT Applications
402(3)
14.5.1 GaN Hybrid Amplifiers
403(1)
14.5.2 GaN MMICs
403(2)
References
405(10)
Chapter 15 Surface Treatment, Fabrication, and Performances of GaN-Based Metal-Oxide-Semiconductor High-Electron Mobility Transistors
415(46)
Ching-Ting Lee
15.1 Introduction
415(2)
15.2 Ohmic Contacts on GaN-Based Semiconductors
417(5)
15.3 Gate Oxides: Materials and Deposition Methods
422(1)
15.4 Surface Treatment of GaN-Based Semiconductors
423(13)
15.4.1 Sulfidation Method
424(6)
15.4.2 Chlorination Method
430(2)
15.4.3 PEC Method
432(4)
15.5 GaN-Based Metal-Oxide-Semiconductor Devices
436(6)
15.6 GaN-Based MOSHEMTs
442(12)
15.7 Conclusions
454(1)
References
454(7)
Chapter 16 GaN-Based HEMTs on Large-Diameter Si Substrate for Next Generation of High Power/High Temperature Devices
461(24)
Farid Medjdoub
16.1 Introduction
461(2)
16.2 GaN-on-Si Devices for High Power at High Frequency
463(5)
16.2.1 DC Characteristics
464(2)
16.2.2 Dynamic Characteristics
466(2)
16.3 GaN on Silicon Devices for Harsh Environment
468(4)
16.4 GaN Power Transistors on Silicon Substrate for Switching Application
472(5)
16.4.1 Ultrathin Barrier Device Design and Fabrication
473(1)
16.4.2 Results and Discussion
474(3)
16.5 Reliability Aspects
477(6)
16.5.1 Thermal Stability Enhancement via In Situ Si3N4 Cap Layer
477(2)
16.5.2 Reliability Test on Power Switching Devices
479(1)
16.5.2.1 Device and Test Description
479(1)
16.5.2.2 Off-State Stress
480(1)
16.5.3 Reliability Test on RF Devices
481(2)
16.6 Conclusions
483(1)
References
483(2)
Chapter 17 GaAs HBT and Power Amplifier Design for Handset Terminals
485(38)
Kazuya Yamamoto
17.1 Introduction
485(1)
17.2 Basics of GaAs-Based HBTs
486(12)
17.2.1 Principle of Operation
486(3)
17.2.2 DC and RF Characteristics
489(4)
17.2.3 Role of Ballasting Resistors and VSWR Ruggedness
493(5)
17.3 Linear Power Amplifier Design for Handset Terminals
498(20)
17.3.1 Basic Bias Circuit Topology
500(3)
17.3.2 Bias Drive and AM-AM/AM-PM Characteristics
503(2)
17.3.3 Bias Circuits and AM-AM/AM-PM Characteristics
505(4)
17.3.4 Harmonic Terminations and AM-AM/AM-PM Characteristics
509(5)
17.3.5 Circuit Design Example for Two-Stage Power Amplifier
514(4)
17.4 Summary
518(1)
References
518(5)
Chapter 18 Resonant Tunneling and Negative Differential Resistance in III-Nitrides
523(22)
Vladimir Litvinov
18.1 Introduction
523(1)
18.2 Single-Layer Devices
524(1)
18.3 Resonant Tunneling Diodes
525(6)
18.3.1 Current-Voltage Characteristics
527(4)
18.4 Superlattices
531(7)
18.4.1 Domain Oscillations and SL-Based High Frequency Sources
532(1)
18.4.2 Conduction Band Profile and Field-Mobility Relation
533(1)
18.4.3 Circuit Design
534(1)
18.4.4 Traveling Electrical Domains
535(1)
18.4.5 Power Oscillations and Their Spectral Content
535(1)
18.4.6 Power Efficiency
536(2)
18.5 Fabrication and DC Characterization of AlxGa1-xN/GaN SL Diodes
538(3)
Acknowledgment
541(1)
References
541(4)
Chapter 19 New Frontiers in Intersubband Optoelectronics Using III-Nitride Semiconductors
545(24)
P. K. Kandaswamy
Eva Monroy
19.1 Introduction to ISB Optoelectronics
545(2)
19.2 III-Nitride Materials for Near-IR Optoelectronics
547(11)
19.2.1 Electronic Structure
548(2)
19.2.2 Growth and Structural Properties
550(2)
19.2.3 Optical Characterization
552(1)
19.2.3.1 IB Characterization
552(1)
19.2.3.2 ISB Absorption
553(1)
19.2.4 Polarization-Induced Doping
554(1)
19.2.5 GaN/A1N Quantum Dots
555(1)
19.2.6 A1InN/GaN System
555(1)
19.2.7 Semipolar III-Nitrides
556(2)
19.2.8 Cubic III-Nitrides
558(1)
19.3 Devices Operating in Near-IR
558(4)
19.3.1 All-Optical Switches
558(1)
19.3.2 Infrared Photodetectors
559(2)
19.3.3 Electro-Optical Modulators
561(1)
19.3.4 Toward Light Emitters
561(1)
19.4 Toward Longer Wavelengths
562(2)
19.5 Conclusions and Perspectives
564(1)
References
564(5)
Index 569
Krzysztof Iniewski is managing R&D developments at Redlen Technologies, Inc., a start-up company in British Columbia, and is also an Executive Director of CMOS Emerging Teclmologies, Inc.
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