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E-raamat: Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications

(Indian Institute of Technology, Roorkee, India), (Indian Institute of Technology-Roorkee, India), (Indian Institute of Technology-Roorkee, India)
  • Formaat: 154 pages
  • Ilmumisaeg: 26-Jun-2017
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781351751032
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Spacer Engineered FinFET Architectures: High-Performance Digital Circuit ApplicationsSuurem pilt
  • Formaat: 154 pages
  • Ilmumisaeg: 26-Jun-2017
  • Kirjastus: CRC Press Inc
  • Keel: eng
  • ISBN-13: 9781351751032
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This book focuses towards the spacer engineering aspects of novel MOS-based device-circuit co-design in sub-20nm technology node, its process complexity, variability and reliabilities issues. This book comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations. This book concentrates on last ten years of cutting-edge research on high-permittivity materials and its usage in FinFETs either as gate-dielectric or spacer engineering. It specifically targets spacer engineering, discussing its pros and cons with FinFETs covers complete device to circuit perspective while exploring its variability aspects also.

Preface ix
About the Authors xiii
Chapter 1 Introduction to Nanoelectronics
1(10)
1.1 Introduction
1(1)
1.2 Scaling and Limitations of a Classical Cmos Device
2(1)
1.3 Potential Technologies Beyond Conventional Cmos
3(1)
1.4 Evolution of Novel Device Structures
4(7)
1.4.1 Planar Double-Gate (DG) MOSFETs
5(1)
1.4.2 FinFET Technology
6(2)
References
8(3)
Chapter 2 Tri-Gate FinFET Technology and Its Advancement
11(26)
2.1 Introduction
11(1)
2.2 3D Tri-Gate/Finfet Technology
12(2)
2.3 FInfet Classification
14(4)
2.3.1 Bulk and Soi Finfets
15(1)
2.3.2 Double-Gate and Tri-Gate FinFETs
15(2)
2.3.3 Tied-Gate and Independent-Gate FinFETs
17(1)
2.3.4 Symmetric and Asymmetric FinFETs
17(1)
2.4 Finfet Fabrication
18(2)
2.5 Technological Restrictions
20(2)
2.6 Review of Advancements in FinFETs
22(5)
2.6.1 Device Structure and Performance Optimization
22(2)
2.6.2 Circuit Design Applications
24(2)
2.6.3 Process Variations
26(1)
2.7 FinFET Design Challenges and Issues
27(2)
2.7.1 High-Permittivity Materials as Spacers
28(1)
2.7.2 Parasitic Resistances and Capacitances
28(1)
2.7.3 SRAM Design Challenges
28(1)
2.8 Summary
29(8)
References
29(8)
Chapter 3 Dual-k Spacer Device Architecture and Its Electrostatics
37(34)
3.1 Introduction
37(3)
3.2 Dual-k Spacer Device Architecture
40(3)
3.3 Tcad Simulation Methodology
43(1)
3.4 Inner High-k Spacer Length Optimization
44(5)
3.4.1 Charge Modulation by Spacer Engineering
44(4)
3.4.2 Effect of Underlap Length
48(1)
3.5 Fabrication Methodology of SymD-k and AsymD-kS FinFETs
49(2)
3.6 Electrostatics and Merits of Dual-k Spacer FinFETs
51(10)
3.6.1 Symmetric Dual-k (SymD-k) Tri-Gate Architecture
51(3)
3.6.2 Asymmetric Dual-k (AsymD-k) Tri-Gate Architecture
54(4)
3.6.3 Dual-k FinFETs with Different Spacer Permittivity
58(3)
3.7 A Comparative Analysis Between Symmetric and Asymmetric Spacer Architectures
61(6)
3.7.1 Source/Drain Spacer Engineering
62(1)
3.7.2 Current Characteristics
63(4)
3.8 Summary
67(4)
References
67(4)
Chapter 4 Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design
71(20)
4.1 Introduction
71(2)
4.2 Impact of Fringe Capacitance on Dual-k FinFETs
73(6)
4.3 Dual-k FinFET-Based Cmos LOGIC Performance: Stability and Speed
79(8)
4.3.1 Static Performance: Noise Margins
80(1)
4.3.2 Dynamic Performance: Delay
81(1)
4.3.2.1 CMOS Inverter
82(2)
4.3.2.2 Three-Stage Ring Oscillator
84(3)
4.4 Effect of Supply Voltage on Dual-k-Based Inverters
87(1)
4.5 Summary
88(3)
References
89(2)
Chapter 5 Design Metric Improvement of a Dual-k-Based SRAM Cell
91(30)
5.1 Introduction
91(2)
5.2 Fundamentals and Evaluation Metrics For an Sram Cell
93(2)
5.3 Design Challenges of FinFET-Based SRAMs
95(1)
5.4 Review of Technology-Circuit Cooptimization of FinFET-BASED SRAMs
96(6)
5.4.1 Source/Drain Asymmetric FinFET-Based SRAM Cells
96(2)
5.4.2 Independent-Gate-Based FinFET SRAMs
98(1)
5.4.3 Fin-Thickness, Fin-Height, and Fin-Ratio Optimization
99(2)
5.4.4 Fabrication Level Optimization
101(1)
5.5 DUAL-k Spacer Engineered Sram CELLS
102(7)
5.5.1 Symmetric Dual-k (SymD-k) FinFET-Based SRAM Cell
102(4)
5.5.2 Asymmetric Dual-k (AsymD-k) FinFET-Based SRAM Cell
106(1)
5.5.2.1 The AsymD-kD FinFET SRAM Configuration
106(1)
5.5.2.2 The AsymD-kS FinFET SRAM Configuration
107(2)
5.6 Effect of Supply Voltage on Dual-k-Based Sram Cells
109(2)
5.7 Symmetric and Asymmetric Dual-k Sram Cell Comparison
111(4)
5.8 Summary
115(6)
References
116(5)
Chapter 6 Statistical Variability and Sensitivity Analysis
121(12)
6.1 Introduction
121(1)
6.2 Impedance Field Method (IFM) and Technology Computer-Aided Design (TCAD) Simulation Setup
122(2)
6.3 Results and Discussions
124(6)
6.3.1 Statistical Variability of SymD-k and AsymD-kS Structures
124(3)
6.3.2 Statistical Variability of SymD-k and AsymD-kS--Based SRAM Cells
127(3)
6.4 Sensitivity Analysis
130(1)
6.5 Summary
131(2)
References
131(2)
Index 133
Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal
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